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MDIO Registers
4.8
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in
Figure 32
and described in
Figure 32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
31
15
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset
Table 30. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
Bit
Field
31-2
Reserved
1
USERACCESS1
0
USERACCESS0
76
EMAC/MDIO Module
Table
30.
Reserved
Reserved
R-0
Field Descriptions
Value
Description
0
Reserved
Masked value of MDIO User command complete interrupt. When asserted, The bit indicates
that the previously scheduled PHY read or write command using that particular
USERACCESS1 register has completed. Writing a 1 will clear the interrupt, writing a 0 has no
effect.
0
No MDIO user command complete event.
1
The previously scheduled PHY read or write command using MDIO user access register
USERACCESS1 has completed and the corresponding bit in USERINTMASKSET is set to 1.
Masked value of MDIO User command complete interrupt. When asserted, The bit indicates
that the previously scheduled PHY read or write command using that particular
USERACCESS0 register has completed. Writing a 1 will clear the interrupt, writing a 0 has no
effect.
0
No MDIO user command complete event.
1
The previously scheduled PHY read or write command using MDIO user access register
USERACCESS0 has completed and the corresponding bit in USERINTMASKSET is set to 1.
© 2011, Texas Instruments Incorporated
R-0
2
www.ti.com
16
1
0
USERACCESS1 USERACCESS0
R/W1C-0
R/W1C-0
SPRUFL5B – April 2011
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