Hc Low-Speed Threshold Register (Hclsthreshold); Hc Low-Speed Threshold Register (Hclsthreshold) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

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3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD)

The HC low-speed threshold register (HCLSTHRESHOLD) defines the latest time in a frame that the
USB1.1 host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in
described in Table
Figure 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD)
31
15 14 13
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions
Bit Field Value
31-14 Reserved
13-0 LST 0-3FFFh
SPRUFM8 – June 2009
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19.
Description
0 Reserved
Low-speed threshold. This field defines the number of full-speed bit times in the frame after which
the USB1.1 host controller cannot start an 8-byte low-speed packet. The USB1.1 host controller
only begins a low-speed transaction if the frame remaining (FR) value in the HC frame remaining
register (HCFMREMAINING) is greater than the low-speed threshold.
The host controller driver must set this field to a value that ensures that an 8-byte low-speed TD
completes before the end of the frame. When set, the host controller driver must not change the
value.
Reserved
R-0
LST
R/W-628h
Universal Serial Bus OHCI Host Controller
Registers
Figure 19 and
16
0
27