Page 1 TMS320C6745/C6747 DSP Technical Reference Manual Literature Number: SPRUH91D March 2013 – Revised September 2016...
Page 2: Table Of Contents
............... 5.3.5 Interrupt Enable Set Register (IENSET) ..............5.3.6 Interrupt Enable Clear Register (IENCLR) ............5.3.7 Fixed Range Start Address Register (FXD_MPSAR) Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 3 Power and Sleep Controller (PSC) ........................ Introduction .................. Power Domain and Module Topology ................... 8.2.1 Power Domain States ....................8.2.2 Module States SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 4 Master Priority Control ......................10.4 Interrupt Support ................10.4.1 Interrupt Events and Requests ................... 10.4.2 Interrupt Multiplexing ................ 10.4.3 Host-DSP Communication Interrupts Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 5 13.4.12 ECAP Interrupt Forcing Register (ECFRC) ................13.4.13 Revision ID Register (REVID) ..........Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) ........................ 14.1 Introduction ...................... 14.1.1 Introduction SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 6 ............15.3.7 eQEP Position Counter Latch Register (QPOSLAT) ................ 15.3.8 eQEP Unit Timer Register (QUTMR) ................ 15.3.9 eQEP Unit Period Register (QUPRD) Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 7 16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers ............16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ......................... 16.5 Tips ....................16.5.1 Debug Checklist ..............16.5.2 Miscellaneous Programming/Debug Tips SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 8 18.2.11 Memory Map ..................18.2.12 Priority and Arbitration ..................18.2.13 System Considerations ..................18.2.14 Power Management ..................18.2.15 Emulation Considerations ....................18.3 Example Configuration Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 9 19.4.7 Performance Counter 2 Register (PC2) ............19.4.8 Performance Counter Configuration Register (PCC) ........19.4.9 Performance Counter Master Region Select Register (PCMRS) SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 10 21.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks .................... 21.2.5 Protocol Description ......................21.2.6 Operation ..................21.2.7 Reset Considerations ...................... 21.2.8 Initialization Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 11 22.3.12 I2C Prescaler Register (ICPSC) ............22.3.13 I2C Revision Identification Register (REVID1) ............22.3.14 I2C Revision Identification Register (REVID2) ..............22.3.15 I2C DMA Control Register (ICDMAC) SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 12 24.1.5 Pin Data Output Register (PDOUT) 1045 ................24.1.6 Pin Data Input Register (PDIN) 1047 ................24.1.7 Pin Data Set Register (PDSET) 1049 Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 13 25.2.1 Clock Control 1097 .................... 25.2.2 Signal Descriptions 1098 ..................25.2.3 Protocol Descriptions 1099 ................ 25.2.4 Data Flow in the Input/Output FIFO 1100 SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 14 Architecture 1149 ....................26.2.1 Clock Source 1149 .................... 26.2.2 Signal Descriptions 1149 ..................26.2.3 Isolated Power Supply 1149 ....................... 26.2.4 Operation 1150 Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 15 1190 ..................27.2.15 Reset Considerations 1192 ..................27.2.16 Power Management 1192 ..................27.2.17 General-Purpose I/O Pin 1193 .................. 27.2.18 Emulation Considerations 1193 SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 16: Purpose Of The Peripheral
28.2.13 Timer Capture Register 34 (CAP34) 1257 .......... 28.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) 1258 ............Universal Asynchronous Receiver/Transmitter (UART) 1260 Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 17: 29.1.3 Functional Block Diagram
30.3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) 1305 ..............30.3.7 HC HCAA Address Register (HCHCCA) 1306 ..........30.3.8 HC Current Periodic Register (HCPERIODCURRENTED) 1306 SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 18 31.4.10 USB Interrupt Source Set Register (INTSETR) 1414 ............31.4.11 USB Interrupt Source Clear Register (INTCLRR) 1415 ..............31.4.12 USB Interrupt Mask Register (INTMSKR) 1416 Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 19 1450 ............31.4.63 Receive Function Address (RXFUNCADDR) 1451 ..............31.4.64 Receive Hub Address (RXHUBADDR) 1451 ................ 31.4.65 Receive Hub Port (RXHUBPORT) 1451 SPRUH91D – March 2013 – Revised September 2016 Contents Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 20 31.4.90 Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) 1469 ......31.4.91 Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) 1470 ........................Revision History 1471 Contents SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 21 7-19. PLL Controller Clock Align Control Register (ALNCTL) ..............7-20. PLLDIV Ratio Change Status Register (DCHANGE) ................7-21. Clock Enable Control Register (CKEN) SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 22 10-24. Pin Multiplexing Control 6 Register (PINMUX6) ..............10-25. Pin Multiplexing Control 7 Register (PINMUX7) ..............10-26. Pin Multiplexing Control 8 Register (PINMUX8) List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 23 13-27. ECAP Interrupt Clear Register (ECCLR) ................13-28. ECAP Interrupt Forcing Register (ECFRC) ................... 13-29. Revision ID Register (REVID) ....................14-1. Multiple ePWM Modules SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 24 14-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ..................14-42. Event-Trigger Interrupt Generator ....................14-43. HRPWM System Interface ............14-44. Resolution Calculations for Conventionally Generated PWM List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 25 ................14-91. Event-Trigger Force Register (ETFRC) ............14-92. Time-Base Phase High-Resolution Register (TBPHSHR) ............14-93. Counter-Compare A High-Resolution Register (CMPAHR) SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 26 16-1. EDMA3 Controller Block Diagram ............16-2. EDMA3 Channel Controller (EDMA3CC) Block Diagram ............16-3. EDMA3 Transfer Controller (EDMA3TC) Block Diagram List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 27 16-50. QDMA Event Missed Register (QEMR) ..............16-51. QDMA Event Missed Clear Register (QEMCR) ................... 16-52. EDMA3CC Error Register (CCERR) SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 28 16-99. Source Active Destination Address B-Reference Register (SADSTBREF) ............16-100. Destination FIFO Set Count Reload Register (DFCNTRLD) ........16-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 29 17-38. MDIO User PHY Select Register 1 (USERPHYSEL1) ................17-39. Transmit Revision ID Register (TXREVID) ................17-40. Transmit Control Register (TXCONTROL) SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 30 17-86. Transmit Channel n Completion Pointer Register (TXnCP) ............17-87. Receive Channel n Completion Pointer Register (RXnCP) ......................17-88. Statistics Register ..................18-1. EMIFA Functional Block Diagram List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 31 .............. 18-49. NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..........18-50. NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 32 ............20-17. GPIO Banks 6 and 7 Set Data Register (SET_DATA67) ..............20-18. GPIO Bank 8 Set Data Register (SET_DATA8) List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 33 21-11. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1: ....................No Autoincrementing) 21-12. UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2: SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 34 22-29. I2C DMA Control Register (ICDMAC) ................. 22-30. I2C Pin Function Register (ICPFUNC) ................... 22-31. I2C Pin Direction Register (ICPDIR) List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 35 23-43. LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) ....................24-1. McASP Block Diagram .................. 24-2. McASP to Parallel 2-Channel DACs SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 36 24-49. Receive Frame Sync Control Register (AFSRCTL) 1063 ..............24-50. Receive Clock Control Register (ACLKRCTL) 1064 ..........24-51. Receive High-Frequency Clock Control Register (AHCLKRCTL) 1065 List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 37 25-17. MMC Control Register (MMCCTL) 1125 ..............25-18. MMC Memory Clock Control Register (MMCCLK) 1126 ................... 25-19. MMC Status Register 0 (MMCST0) 1127 SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 38 26-23. Scratch Registers (SCRATCHn) 1170 ....................26-24. Kick Registers (KICKnR) 1170 ...................... 27-1. SPI Block Diagram 1173 ......................27-2. SPI 3-Pin Option 1179 List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 39 1241 ................28-10. Watchdog Timer Operation State Diagram 1241 ................28-11. Timer Operation in Pulse Mode (CPn = 0) 1243 SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 40 30-5. HC Interrupt and Status Register (HCINTERRUPTSTATUS) 1303 ............30-6. HC Interrupt Enable Register (HCINTERRUPTENABLE) 1304 ............30-7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) 1305 List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 41 1408 ................... 31-30. Emulation Register (EMUR) 1408 ....................31-31. Mode Register (MODE) 1409 .................. 31-32. Auto Request Register (AUTOREQ) 1411 SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 42 31-79. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) 1446 ................... 31-80. Device Control Register (DEVCTL) 1446 ................31-81. Transmit Endpoint FIFO Size (TXFIFOSZ) 1447 List of Figures SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 43 31-116. Queue Manager Queue N Status Register B (QSTATB[N]) 1469 ............. 31-117. Queue Manager Queue N Status Register C (QSTATC[N]) 1470 SPRUH91D – March 2013 – Revised September 2016 List of Figures Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 44 ........... 7-14. PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions ........... 7-15. PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 45 10-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions ..........10-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ..........10-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 46 13-11. ECAP2 Initialization for Multichannel PWM Generation with Phase Control ........13-12. ECAP3 Initialization for Multichannel PWM Generation with Phase Control ..................13-13. Control and Status Register Set List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 47 14-34. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ....................14-35. EPWM1 Initialization for ....................14-36. EPWM2 Initialization for SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 48 14-83. Event-Trigger Force Register (ETFRC) Field Descriptions ................. 14-84. High-Resolution PWM Submodule Registers ........14-85. Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 49 16-18. Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ............... 16-19. C Count Parameter (CCNT) Field Descriptions ..............16-20. EDMA3 Channel Controller (EDMA3CC) Registers SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 50 16-67. Error Clear Register (ERRCLR) Field Descriptions ..............16-68. Error Details Register (ERRDET) Field Descriptions ..........16-69. Error Interrupt Command Register (ERRCMD) Field Descriptions List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 51 17-26. PHY Link Status Register (LINK) Field Descriptions ....17-27. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 52 ..........17-74. MAC Hash Address Register 1 (MACHASH1) Field Descriptions ..........17-75. MAC Hash Address Register 2 (MACHASH2) Field Descriptions List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 53 18-36. EMIFA Timing Requirements for TC5516100FT-12 Example ............. 18-37. ASRAM Timing Requirements for TC5516100FT-12 Example ............. 18-38. Measured PCB Delays for TC5516100FT-12 Example SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 54 19-15. Example Mapping from Logical Address to EMIFB Pins for 16-bit SDRAM ........19-16. Example Mapping from Logical Address to EMIFB Pins for mobile SDRAM List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 55 21-9. GPIO Enable Register (GPIO_EN) Field Descriptions ............21-10. GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions ............21-11. GPIO Data 1 Register (GPIO_DAT1) Field Descriptions SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 56 23-15. LCD LIDD CSn Configuration Register (LIDD_CSn_CONF) Field Descriptions ......23-16. LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR) Field Descriptions List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 57 24-38. Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions 1078 ............ 24-39. Transmit TDM Time Slot Register (XTDM) Field Descriptions 1079 SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 58 1158 ................26-8. Year Register (YEAR) Field Descriptions 1159 ............. 26-9. Day of the Week Register (DOTW) Field Descriptions 1159 List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 59 28-6. TSTAT Parameters in Pulse and Clock Modes 1243 ..................28-7. Timer Emulation Modes Selection 1245 ......................28-8. Timer Registers 1245 SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 60 ........30-6. HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions 1304 ........30-7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions 1305 List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 61 31-30. Universal Serial Bus OTG (USB0) Registers 1400 ............31-31. Revision Identification Register (REVID) Field Descriptions 1407 ............... 31-32. Control Register (CTRLR) Field Descriptions 1407 SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 62 31-80. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions 1444 ......31-81. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions 1445 List of Tables SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 63 31-120. Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions 1469 ....... 31-121. Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions 1470 SPRUH91D – March 2013 – Revised September 2016 List of Tables Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 64: Preface
CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory. Code Composer Studio is a trademark of Texas Instruments. SD is a trademark of SanDisk Corporation.
Page 65 Chapter 1 SPRUH91D – March 2013 – Revised September 2016 Overview ........................... Topic Page ....................... Introduction SPRUH91D – March 2013 – Revised September 2016 Overview Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 66: Introduction
SDRAM Only OTG Ctlr MDIO NAND/Flash (8b) (RMII) (16b) Note: Not all peripherals are available at the same time due to multiplexing. Overview SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 67 OHCI Ctlr MDIO NAND/Flash (8b) (RMII) (16b/32b) 16b SDRAM Note: Not all peripherals are available at the same time due to multiplexing. SPRUH91D – March 2013 – Revised September 2016 Overview Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 68: Dsp Subsystem
SPRUH91D – March 2013 – Revised September 2016 DSP Subsystem ........................... Topic Page ....................... Introduction ................. TMS320C674x Megamodule ...................... Memory Map ................ Advanced Event Triggering (AET) DSP Subsystem SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 69: Tms320C674X Megamodule Block Diagram
B Bandwidth Mgmt Configuration peripherals Memory protect Cache control MDMA SDMA 8x32 32K bytes High performance L1D RAM/ switch fabric cache SPRUH91D – March 2013 – Revised September 2016 DSP Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 70: Dsp Interrupt Map
C674x Interrupt Control 1 EVT2 C674x Interrupt Control 2 EVT3 C674x Interrupt Control 3 T64P0_TINT12 Timer64P0 - TINT12 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register DSP Subsystem SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 71 Reserved ECAP2 ECAP2 This peripheral is not supported on the C6745 DSP. This peripheral is not supported on the C6745 DSP. SPRUH91D – March 2013 – Revised September 2016 DSP Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 72 Timer64P1 - Compare 7 94-95 — Reserved INTERR C674x-Interrupt Control EMC_IDMAERR C674x-EMC 98-112 — Reserved PMC_ED C674x-PMC 114-115 — Reserved UMC_ED1 C674x-UMC DSP Subsystem SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 73 Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and all internal memories immediately upon command from software. SPRUH91D – March 2013 – Revised September 2016 DSP Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 74: Memory Map
See the System Interconnect chapter and the System Memory chapter for a description of the additional system memory and peripherals that the DSP has access to. DSP Subsystem SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 75: Advanced Event Triggering (Aet)
Counters: count the occurrence of an event or cycles for performance monitoring. • State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences. SPRUH91D – March 2013 – Revised September 2016 DSP Subsystem Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 76: System Interconnect
Chapter 3 SPRUH91D – March 2013 – Revised September 2016 System Interconnect ........................... Topic Page ....................... Introduction ..............System Interconnect Block Diagram System Interconnect SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 77: Tms320C6745/C6747 Dsp System Interconnect Matrix
The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level. SPRUH91D – March 2013 – Revised September 2016 System Interconnect Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 78: System Interconnect Block Diagram
Paths with dashed lines cross the subchip boundary eQEP0 eQEP1 EDMA3 CC EDMA3 CC This peripheral is not supported on the C6745 DSP. System Interconnect SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 79: System Memory
Chapter 4 SPRUH91D – March 2013 – Revised September 2016 System Memory ........................... Topic Page ....................... Introduction ....................DSP Memories ......................Peripherals SPRUH91D – March 2013 – Revised September 2016 System Memory Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 80: Introduction
Bandwidth manager (BWM) • Internal DMA (IDMA) For more information on these internal peripherals, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). System Memory SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 81: Peripherals
The DSP has access to all peripherals on the device. See the device-specific data manual for the complete list of peripherals supported on your device. SPRUH91D – March 2013 – Revised September 2016 System Memory Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 82: Memory Protection Unit (Mpu)
SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) ........................... Topic Page ....................... Introduction ....................... Architecture ....................MPU Registers Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 83: Mpu Block Diagram
(MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT). Figure 5-1. MPU Block Diagram Input Output Protection Data Data Checks MPU_ADDR_ERR_INT MMRs MPU_PROT_ERR_INT MPU Register Bus SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 84: Mpu Memory Regions
In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 85: Device Master Settings
MPU. The MPU can be configured for “assumed allowed” or “assumed disallowed” mode as dictated by the ASSUME_ALLOWED bit in the configuration register (CONFIG). SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 86: Permission Fields
Description Supervisor may read Supervisor may write Supervisor may execute User may read User may write User may execute Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 87: Protection Check
Faults are not recorded (nor interrupts generated) for debug accesses. SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 88: Mpu_Bootcfg_Err Interrupt Sources
MPU1 is not supported on the C6745 DSP. 5.2.10 Emulation Considerations Memory and MPU registers are not protected against emulation accesses. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 89: Memory Protection Unit 1 (Mpu1) Registers
Fixed range end address register Section 5.3.8 01E1 5108h FXD_MPPA Fixed range memory protection page attributes register Section 5.3.9 SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 90 Fault address register Section 5.3.13 01E1 5304h FLTSTAT Fault status register Section 5.3.14 01E1 5308h FLTCLR Fault clear register Section 5.3.15 Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 91: Revision Id Register (Revid)
Assume allowed. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not allowed. Assume is disallowed. Assume is allowed. SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 92: Interrupt Raw Status/Set Register (Irawstat)
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 93: Interrupt Enable Status/Clear Register (Ienstat)
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 94: Interrupt Enable Set Register (Ienset)
Writing 0 has no effect. Interrupt is cleared/disabled. PROTERR_CLR Protection violation error disable. Writing 0 has no effect. Interrupt is cleared/disabled. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 95: Fixed Range End Address Register (Fxd_Mpear)
Figure 5-10. Fixed Range End Address Register (FXD_MPEAR) Reserved LEGEND: R = Read only; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 96: Fixed Range Memory Protection Page Attributes Register (Fxd_Mppa)
Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 97: Programmable Range N Start Address Registers (Progn_Mpsar)
Table 5-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions Field Value Description 31-16 START_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved Reserved SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 98: Programmable Range N End Address Registers (Progn_Mpear)
Table 5-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions Field Value Description 31-16 END_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved FFFFh Reserved Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 99: Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 100: Fault Address Register (Fltaddrr)
Table 5-20. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Memory address of fault. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 101: Fault Status Register (Fltstat)
Supervisor write fault. Reserved Relaxed cache write back fault. 13h-1Fh Reserved Supervisor read fault. 21h-3Eh Reserved Relaxed cache line fill fault. SPRUH91D – March 2013 – Revised September 2016 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 102: Fault Clear Register (Fltclr)
Reserved CLEAR Command to clear the current fault. Writing 0 has no effect. No effect. Clear the current fault. Memory Protection Unit (MPU) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 103: Device Clocking
SPRUH91D – March 2013 – Revised September 2016 Device Clocking ........................... Topic Page ......................Overview ..................Frequency Flexibility ..................Peripheral Clocking SPRUH91D – March 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 104: Overview
This peripheral is not supported on the C6745 DSP. McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745 DSP. Device Clocking SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 105: Frequency Flexibility
SYSCLK has a PLLDIV block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter for more details on the PLL. SPRUH91D – March 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 106: Example Pll Frequencies
CPU frequency of 200 MHz. Table 6-3. Example PLL Frequencies Multiplier OSCIN Frequency Frequency PLL Multiplier (MHz) Div1 Div2 Div3 Div4 112.5 Device Clocking SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 107: Peripheral Clocking
CLK48MHz From USB2.0 PHY CFGCHIP2[USB1PHYCLKMUX] CLK48 CLK12 USB 1.1 Subsystem (USB1) Note: The USB1.1 is not supported on the C6745 DSP. SPRUH91D – March 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 108: Usb Clock Multiplexing Options
38.4, 13, 26, 20, or 40 MHz. The PLL inside the USB2.0 PHY can be configured to accept any of these input clock frequencies. USB_REFCLKIN must be 48 MHz. Device Clocking SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 109: 6.3.2 Emifb Clocking
EMIFB via the LPSC while still providing a clock on the EMB_CLK. NOTE: EMB_CLK is only an output clock. EMIFB does not support an externally provided input clock. SPRUH91D – March 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 110: Emifb Clocking Diagram
133 MHz 89 MHz 133 MHz Div4 100 MHz 89 MHz 133 MHz Section 6.2 for an explanation of POSTDIV divider modes. Device Clocking SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 111: 6.3.3 Emifa Clocking
133 MHz 89 MHz 66.5 MHz Div4 100 MHz 89 MHz 100 MHz Section 6.2 for explanation of POSTDIV divider modes. SPRUH91D – March 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 112: 6.3.4 Emac Clocking
0000 0010 RMII_MHZ_50_CLK Signal NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. Device Clocking SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 113: Emac Reference Clock Frequencies
Not Applicable Section 6.2 for explanation of POSTDIV divider modes. Certain PLL configurations do not support a 50 MHz clock on SYSCLK7. SPRUH91D – March 2013 – Revised September 2016 Device Clocking Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 114: 6.3.5 I/O Domains
This peripheral is not supported on the C6745 DSP. McASP2 is not supported on the C6745 DSP; only McASP0 and McASP1 are supported on the C6745 DSP. Device Clocking SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 115: Phase-Locked Loop Controller (Pllc)
Phase-Locked Loop Controller (PLLC) ........................... Topic Page ..................... Introduction ....................PLL0 Control ............. Locking/Unlocking PLL Register Access ....................PLLC Registers SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 116: Introduction
PLL mode operation (set the PLLEN bit in PLLCTL to 1). Registers used in PLLC0 are listed in Section 7.4. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 117: Pll0 Structure
OBSCLK Pin SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 OCSEL[OCSRC] This register is not supported on the C6745 DSP. SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 118: 7.2.1 Device Clock Generation
The DIV4P5 (/4.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. See Figure 7-1. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 119: 7.2.2 Steps For Changing Pll0 Domain Frequency
8. Wait for PLL to lock. See the device-specific data manual for PLL lock time. 9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode. SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 120: Locking/Unlocking Pll Register Access
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 defaults to unlocked after reset, so the above procedure is only required after the PLL_MASTER_LOCK bit has been locked (set to 1). Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 121: Pllc Registers
01C1 11F4h EMUCNT1 Emulation Performance Counter 1 Register Section 7.4.24 This register is not supported on the C6745 DSP. SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 122: Revision Identification Register (Revid)
Power On Reset (POR) was not the last reset to occur. Power On Reset (POR) was the last reset to occur. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 123: Pll Control Register (Pllctl)
Reserved Reserved PLLPWRDN PLL power-down. PLL operation PLL power-down PLLEN PLL mode enables. Bypass mode PLL mode, not bypassed SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 124: Obsclk Select Register (Ocsel)
OSCIN 15h-16h Reserved PLLC0 SYSCLK1 PLLC0 SYSCLK2 PLLC0 SYSCLK3 PLLC0 SYSCLK4 PLLC0 SYSCLK5 PLLC0 SYSCLK6 PLLC0 SYSCLK7 Reserved Disabled Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 125: Pll Multiplier Control Register (Pllm)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1). SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 126: Pll Controller Divider 1 Register (Plldiv1)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2). Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 127: Pll Controller Divider 3 Register (Plldiv3)
Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4). SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 128: Pll Controller Divider 5 Register (Plldiv5)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1). Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 129: Pll Controller Divider 7 Register (Plldiv7)
Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6). SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 130: Oscillator Divider 1 Register (Oscdiv)
RATIO 0-1Fh Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 131: Pll Post-Divider Control Register (Postdiv)
Field Value Description 31-1 Reserved Reserved GOSET GO bit for SYSCLKx phase alignment. Clear bit (no effect) Phase alignment SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 132: Pll Controller Status Register (Pllstat)
Status of GO operation. If 1, indicates GO operation is in progress. GO operation is not in progress. GO operation is in progress. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 133: Pll Controller Clock Align Control Register (Alnctl)
SYSCLK2 needs to be aligned to others selected in this register. ALN1 SYSCLK1 needs to be aligned to others selected in this register. SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 134: Plldiv Ratio Change Status Register (Dchange)
Ratio is not modified. Ratio is modified. SYS1 SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 135: Clock Enable Control Register (Cken)
AUXCLK enable. Actual AUXCLK status is shown in the clock status register (CKSTAT). AUXCLK is disabled. AUXCLK is enabled. SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 136: Clock Status Register (Ckstat)
AUXCLK on status. AUXCLK is controlled by the AUXEN bit in the clock enable control register (CKEN). AUXCLK is off. AUXCLK is on. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 137: Sysclk Status Register (Systat)
SYSCLK5 on status SYS4ON SYSCLK4 on status SYS3ON SYSCLK3 on status SYS2ON SYSCLK2 on status SYS1ON SYSCLK1 on status SPRUH91D – March 2013 – Revised September 2016 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 138: Emulation Performance Counter 0 Register (Emucnt0)
Table 7-26. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions Field Value Description 31-0 COUNT 0-FFFF FFFFh Counter value for upper 64-bits. Phase-Locked Loop Controller (PLLC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 139: Power And Sleep Controller (Psc)
Power Domain and Module Topology ................Executing State Transitions ..............IcePick Emulation Support in the PSC ....................PSC Interrupts ....................PSC Registers SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 140: Introduction
— — — UART0 AlwaysON (PD0) SwRstDisable — Not Used — — — SCR1 (BR4) AlwaysON (PD0) Enable Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 141: Psc1 Default Module Configuration
Not Used — — — Shared RAM (BR13) PD_SHRAM Enable This peripheral is not supported on the C6745 DSP. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 142: 8.2.1 Power Domain States
Disable, SyncReset, or SwRstDisable state the power sleep controller ignores these transition requests and transitions the module state to Enable. Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 143: Module States
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset. If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 144: Executing State Transitions
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only after the GOSTAT[x] bit in PTSTAT is cleared to 0. Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 145: Icepick Emulation Support In The Psc
NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 146: 8.5.2 Interrupt Registers
(MERRCR0), or the bit corresponding to the power domain number in the power error clear register (PERRCR) in PSC0 module. Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 147: 8.5.3 Interrupt Handling
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt controller, if there are still any active interrupt events. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 148: Psc Registers
Section 8.6.17 01E2 787Ch MDSTAT31 01E2 7A00h- MDCTL0- Module Control n Register (modules 0-31) Section 8.6.19 01E2 7A7Ch MDCTL31 Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 149: Revision Identification Register (Revid)
Evaluate PSC interrupt (PSCn_ALLINT). A write of 0 has no effect. A write of 1 re-evaluates the interrupt condition. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 150: Psc0 Module Error Pending Register 0 (Modules 0-15) (Merrpr0)
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0) Reserved LEGEND: R = Read only; -n = value after reset Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 151: Psc0 Module Error Clear Register 0 (Modules 0-15) (Merrcr0)
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0) Reserved LEGEND: R = Read only; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 152: Power Error Pending Register (Perrpr)
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1. Reserved Reserved Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 153: Power Domain Transition Command Register (Ptcmd)
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching the corresponding current state (MDSTAT.STATE), the PSC will transition those respective domain/modules to the new NEXT state. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 154: Power Domain Transition Status Register (Ptstat)
No transition in progress. Modules in Always ON power domain are transitioning. Always On power domain is transitioning. Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 155: Power Domain 0 Status Register (Pdstat0)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 156: Power Domain 1 Status Register (Pdstat1)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 157: Power Domain 0 Control Register (Pdctl0)
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect since internally this power domain always remains in the on state. Power domain off. Power domain on. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 158: Power Domain 1 Control Register (Pdctl1)
Enable interrupt. Reserved Reserved Reserved Reserved NEXT User-desired power domain next state. Power domain off. Power domain on. Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 159: Power Domain 0 Configuration Register (Pdcfg0)
RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 160: Power Domain 1 Configuration Register (Pdcfg1)
RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 161: Module Status N Register (Mdstatn)
Module state status: indicates current module status. SwRstDisable state SyncReset state Disable state Enable state 4h-3Fh Indicates transition SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 162: Psc0 Module Control N Register (Modules 0-15) (Mdctln)
De-assert local reset Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state Power and Sleep Controller (PSC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 163: Psc1 Module Control N Register (Modules 0-31) (Mdctln)
Force is enabled. 30-3 Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state SPRUH91D – March 2013 – Revised September 2016 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 164: Power Management
PSC and PLLC Overview ......................Features ................... Clock Management ................DSP Sleep Mode Management ....................RTC-Only Mode ........Additional Peripheral Power Management Considerations Power Management SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 165: Introduction
For detailed information on the PSC, see the Power and Sleep Controller (PSC) chapter. For detailed information on the PLLC, see the Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter. SPRUH91D – March 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 166: Features
The USB2.0 Phy can be powered-down. Minimizes USB2.0 I/O power consumption when not in use. This peripheral is not supported on the C6745 DSP. Power Management SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 167: Clock Management
PLL module. The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass and PLL power down. SPRUH91D – March 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 168: Dsp Sleep Mode Management
RTC module, running at 32 kHz. NOTE: The RTC is not supported on the C6745 DSP. Power Management SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 169: Additional Peripheral Power Management Considerations
SDRAM interface, it is recommended to use CLK1 as the source, as it allows maximal power savings (clock gating both VCLK/MCLK and EMB_CLK signal) via the PSC. SPRUH91D – March 2013 – Revised September 2016 Power Management Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 170: System Configuration (Syscfg) Module
..................... 10.1 Introduction ......................10.2 Protection ..................10.3 Master Priority Control ....................10.4 Interrupt Support .................... 10.5 SYSCFG Registers System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 171: 10.1 Introduction
• Several registers in the module are only accessible when the CPU requesting read/write access is in privileged mode. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 172: 10.2 Protection
Chip Signal Register — 178h CHIPSIG_CLR Chip Signal Clear Register — 17Ch-18Ch CFGCHIP0-CFGCHIP4 Chip Configuration 0-4 Registers Privileged mode System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 173: 10.2.1 Requirements To Access Syscfg Registers
After steps 1 and 2, the SYSCFG module registers are accessible and can be configured as per the application requirements. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 174: 10.3 Master Priority Control
Reserved 38-63 Reserved EMAC USB1.1 66-95 Reserved LCDC 97-255 Reserved This peripheral is not supported on the C6745 DSP. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 175: 10.4 Interrupt Support
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 176: 10.5 Syscfg Registers
Pin Multiplexing Control 19 Register Section 10.5.10.20 01C1 4170h SUSPSRC Suspend Source Register Section 10.5.11 This register is for internal-use only. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 177: Revision Identification Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions Field Value Description 31-0 DEVID0 R-0B7D F02Fh Device identification. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 178: Boot Configuration Register (Bootcfg)
Field Value Description 31-4 Reserved Reserved CHIPREV Identifies silicon revision of device. 0-3h Older silicon revision Silicon revision 3.0 System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 179: Kick Registers (Kick0R-Kick1R)
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written before writing to the kick1 register. Writing any other value will lock the other MMRs. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 180: Host 1 Configuration Register (Host1Cfg)
DSP boot ready bit allowing DSP to boot. DSP held in reset mode. DSP released from wait in reset mode. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 181: 10.5.7 Interrupt Registers
Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 sets the status. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 182: Interrupt Enable Status/Clear Register (Ienstat)
Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 clears the status. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 183: Interrupt Enable Register (Ienset)
Writing a 1 clears/disables this interrupt. PROTERR_CLR Protection violation error. Writing a 0 has not effect. Writing a 1 clears/disables this interrupt. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 184: 10.5.8 Fault Registers
Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Fault address for the first fault transfer. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 185: Fault Status Register (Fltstat)
User read fault 5h-7h Reserved Supervisor execute fault 9h-Fh Reserved Supervisor write fault 11h-1Fh Reserved Supervisor read fault 21h-3Fh Reserved SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 186: Master Priority Registers (Mstpri0-Mstpri2)
Reserved. Write the default value when modifying this register. Reserved Reserved. Always read as 0. Reserved Reserved. Write the default value when modifying this register. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 187: Master Priority 1 Register (Mstpri1)
Reserved. Always read as 0. PRU0 0-7h PRU0 priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 188: Master Priority 2 Register (Mstpri2)
Reserved. Write the default value when modifying this register. EMAC 0-7h EMAC priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 189: Pin Multiplexing Control Registers (Pinmux0-Pinmux19)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 190 Reserved Selects Function GP7[14] 2h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 191: Pin Multiplexing Control 1 Register (Pinmux1)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 192 Selects Function GP7[1] 9h-Fh Reserved PINMUX1_3_0 EMB_BA[1]/GP7[0] Control Pin is 3-stated. Selects Function EMB_BA[1] 2h-7h Reserved Selects Function GP7[0] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 193: Pin Multiplexing Control 2 Register (Pinmux2)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 194 Selects Function GP7[9] 9h-Fh Reserved PINMUX2_3_0 EMB_A[6]/GP7[8] Control Pin is 3-stated. Selects Function EMB_A[6] 2h-7h Reserved Selects Function GP7[8] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 195: Pin Multiplexing Control 3 Register (Pinmux3)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 196: Pin Multiplexing Control 4 Register (Pinmux4)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 197: Pin Multiplexing Control 5 Register (Pinmux5)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 198 2h-7h Reserved Selects Function GP6[0] 9h-Fh Reserved PINMUX5_3_0 — EMB_WE_DQM[2] Control Pin is 3-stated. Selects Function EMB_WE_DQM[2] 2h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 199: Pin Multiplexing Control 6 Register (Pinmux6)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 200 Selects Function GP6[8] 9h-Fh Reserved PINMUX6_3_0 EMB_D[7]/GP6[7] Control Pin is 3-stated. Selects Function EMB_D[7] 2h-7h Reserved Selects Function GP6[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 201: Pin Multiplexing Control 7 Register (Pinmux7)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 202 Selects Function GP5[14] 9h-Fh Reserved PINMUX7_3_0 EMB_D[15]/GP6[15] Control Pin is 3-stated. Selects Function EMB_D[15] 2h-7h Reserved Selects Function GP6[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 203: Pin Multiplexing Control 8 Register (Pinmux8)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 204 PINMUX8_3_0 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] Control Pin is 3-stated. Selects Function SPI1_SOMI[0] Selects Function I2C1_SCL 3h-7h Reserved Selects Function GP5[5] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 205: Pin Multiplexing Control 9 Register (Pinmux9)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 206 PINMUX9_3_0 SPI1_SCS[0]/UART2_TXD/GP5[13] Control Pin is 3-stated. Selects Function SPI1_SCS[0] Selects Function UART2_TXD 3h-7h Reserved Selects Function GP5[13] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 207: Pin Multiplexing Control 10 Register (Pinmux10)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 208 9h-Fh Reserved PINMUX10_3_0 — AMUTE0/RESETOUT Control Selects Function RESETOUT Selects Function AMUTE0 2h-7h Reserved Selects Function RESETOUT 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 209: Pin Multiplexing Control 11 Register (Pinmux11)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 210 PINMUX11_3_0 AXR0[7]/MDIO_CLK/GP3[7] Control Pin is 3-stated. Selects Function AXR0[7] Selects Function MDIO_CLK 3h-7h Reserved Selects Function GP3[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 211: Pin Multiplexing Control 12 Register (Pinmux12)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 212 9h-Fh Reserved PINMUX12_3_0 — AHCLKR1/GP4[11] Control Pin is 3-stated. Selects Function AHCLKR1 2h-7h Reserved Selects Function GP4[11] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 213: Pin Multiplexing Control 13 Register (Pinmux13)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 214 PINMUX13_3_0 AXR1[4]/EQEP1B/GP4[4] Control Pin is 3-stated. Selects Function AXR1[4] Selects Function EQEP1B 3h-7h Reserved Selects Function GP4[4] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 215: Pin Multiplexing Control 14 Register (Pinmux14)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 216 Pin is 3-stated. Selects Function EMA_D[2] Selects Function MMCSD_DAT[2] Reserved Selects Function UHPI_HD[2] 5h-7h Reserved Selects Function GP0[2] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 217: Pin Multiplexing Control 15 Register (Pinmux15)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 218 Pin is 3-stated. Selects Function EMA_D[10] Selects Function UHPI_HD[10] Reserved Selects Function LCD_D[10] 5h-7h Reserved Selects Function GP0[10] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 219: Pin Multiplexing Control 16 Register (Pinmux16)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 220 Pin is 3-stated. Selects Function EMA_A[2] Selects Function MMCSD_CMD Reserved Selects Function UHPI_HCNTL1 5h-7h Reserved Selects Function GP1[2] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 221: Pin Multiplexing Control 17 Register (Pinmux17)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 222 PINMUX17_3_0 EMA_A[10]/LCD_VSYNC/GP1[10] Control Pin is 3-stated. Selects Function EMA_A[10] Selects Function LCD_VSYNC 3h-7h Reserved Selects Function GP1[10] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 223: Pin Multiplexing Control 18 Register (Pinmux18)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 224 — EMA_RAS/EMA_CS[5]/GP2[2] Control Pin is 3-stated. Selects Function EMA_RAS Selects Function EMA_CS[5] 3h-7h Reserved Selects Function GP2[2] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 225: Pin Multiplexing Control 19 Register (Pinmux19)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 226: Suspend Source Register (Suspsrc)
DSP is the source of the emulation suspend. SPI0SRC SPI0 Emulation Suspend Source. No emulation suspend. DSP is the source of the emulation suspend. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 227 DSP is the source of the emulation suspend. ECAP0SRC ECAP0 Emulation Suspend Source. No emulation suspend. DSP is the source of the emulation suspend. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 228: Chip Signal Register (Chipsig)
Asserts SYSCFG_CHIPINT2 interrupt. No effect Asserts interrupt Reserved Reserved. Write the default value to all bits when modifying this register. System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 229: Chip Signal Clear Register (Chipsig_Clr)
Clears SYSCFG_CHIPINT2 interrupt. No effect Clears interrupt Reserved Reserved. Write the default value to all bits when modifying this register. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 230: Chip Configuration 0 Register (Cfgchip0)
16 bytes 32 bytes 64 bytes Reserved TC0DBS TC0 Default Burst Size (DBS). 16 bytes 32 bytes 64 bytes Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 231: Chip Configuration 1 Register (Cfgchip1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset This bit is not supported and is Reserved on the C6745 DSP. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 232: Chip Configuration 1 Register (Cfgchip1) Field Descriptions
EMAC C2 RX Threshold Pulse Interrupt EMAC C2 RX Pulse Interrupt EMAC C2 TX Pulse Interrupt EMAC C2 Miscellaneous Interrupt 13h-1Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 233 GPIO Interrupt from Bank 4 GPIO Interrupt from Bank 5 GPIO Interrupt from Bank 6 GPIO Interrupt from Bank 7 9h-Fh Reserved SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 234 GPIO Interrupt from Bank 4 GPIO Interrupt from Bank 5 GPIO Interrupt from Bank 6 GPIO Interrupt from Bank 7 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 235: Chip Configuration 2 Register (Cfgchip2)
USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin. USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL. SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 236 12 MHz 24 MHz 48 MHz 19.2 MHz 38.4 MHz 13 MHz 26 MHz 20 MHz 40 MHz Ah-Fh Reserved System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 237: Chip Configuration 3 Register (Cfgchip3)
Clock driven by DIV4.5 PLL output EMB_CLKSRC Clock source for EMIFB clock domain. Clock driven by PLLC SYSCLK5 Clock driven by DIV4.5 PLL output SPRUH91D – March 2013 – Revised September 2016 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 238: Chip Configuration 4 Register (Cfgchip4)
Clears the 'latched' GPIO interrupt for AMUTEIN of McASP0 when set to 1. The AMUTE0 signal is not supported on the C6745 DSP. No effect Clears interrupt System Configuration (SYSCFG) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 239: Boot Considerations
Chapter 11 SPRUH91D – March 2013 – Revised September 2016 Boot Considerations ........................... Topic Page ..................... 11.1 Introduction SPRUH91D – March 2013 – Revised September 2016 Boot Considerations Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 240: 11.1 Introduction
See Using the C6747/45/43 Bootloader Application Report (SPRABB1) for more details on the ROM Boot Loader, a list of boot pins used, and the complete list of supported boot modes. Boot Considerations SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 241: Programmable Real-Time Unit Subsystem (Pruss)
Chapter 12 SPRUH91D – March 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) ........................... Topic Page SPRUH91D – March 2013 – Revised September 2016 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 242 The PRUSS documentation (peripheral guide) is on the external wiki: Programmable_Realtime_Unit. Programmable Real-Time Unit Subsystem (PRUSS) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 243: Enhanced Capture (Ecap) Module
This chapter describes the eCAP module..........................Topic Page ..................... 13.1 Introduction ..................... 13.2 Architecture ....................13.3 Applications ......................13.4 Registers SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 244: 13.1 Introduction
• When not used in capture mode, the ECAP module can be configured as a single channel PWM output Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 245: 13.2 Architecture
ECAP1INT SyncOut SyncIn ECAP2/ ECAP2 APWM2 GPIO Interrupt module Controller ECAP2INT SyncOut SyncIn ECAPx/ ECAPx APWMx module ECAPxINT SyncOut SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 246: 13.2.1 Capture And Apwm Operating Mode
(2) In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes the shadow mode. Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 247: 13.2.2 Capture Mode Description
Oneshot Controller CTR_OVF Capture Control Flag CTR=PRD control CTR=CMP ECCTL2 [ RE-ARM, CONT/ONESHT, STOP_WRAP] Registers: ECEINT, ECFLG, ECCLR, ECFRC SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 248: Event Prescale Control
Figure 13-5. Prescale Function Waveforms ECAPx PSout div 2 PSout div 4 PSout div 6 PSout div 8 PSout div 10 Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 249: Continuous/One-Shot Block Diagram
2:4 MUX CEVT1 CEVT2 Modulo 4 CEVT3 Stop counter CEVT4 Mod_eq One−shot control logic Stop value (2b) ECCTL2[STOP_WRAP] ECCTL2[RE−ARM] ECCTL2[CONT/ONESHT] SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 250: Counter And Synchronization Block Diagram
ECCTL2[SYNCOSEL] SYNCI CTR=PRD Disable SYNCO Disable ECCTL2[SYNCI_EN] Sync out select CTRPHS LD_CTRPHS Delta−mode TSCTR (counter 32b) SYSCLK CTR−OVF CTR[31−0] Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 251 (ECCTL2[CAP/APWM == 0]). The CTR = PRD, CTR = CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes. SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 252: Interrupts In Ecap Module
ECCLR ECFRC Latch CTROVF ECEINT ECFLG Clear ECCLR ECFRC Latch ECEINT PRDEQ ECFLG Clear ECCLR ECFRC Latch ECEINT CMPEQ Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 253: Pwm Waveform Details Of Apwm Mode Operation
CMP = PERIOD, output low except for 1 cycle (<100% duty) CMP = PERIOD+1, output low for complete period (100% duty) SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 254: 13.3 Applications
#define EC_CAP_MODE #define EC_APWM_MODE // APWMPOL bit #define EC_ACTV_HI #define EC_ACTV_LO // Generic #define EC_DISABLE #define EC_ENABLE #define EC_FORCE Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 255: Absolute Time-Stamp Operation Rising Edge Trigger Example
CAP1 CAP2 CAP3 CAP4 All capture values valid Polarity selection (can be read) at this time Capture registers [1−4] SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 256: Ecap Initialization For Cap Mode Absolute Time, Rising Edge Trigger
Period1 = TSt2-TSt1; // Calculate 1st period Period2 = TSt3-TSt2; // Calculate 2nd period Period3 = TSt4-TSt3; // Calculate 3rd period Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 257: 13.3.2 Absolute Time-Stamp Operation Rising And Falling Edge Trigger Example
CEVT3 CEVT1 CEVT3 CEVT1 CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 258: Ecap Initialization For Cap Mode Absolute Time, Rising And Falling Edge Trigger
Period1 = TSt3-TSt1; // Calculate 1st period DutyOnTime1 = TSt2-TSt1; // Calculate On time DutyOffTime1 = TSt3-TSt2; // Calculate Off time Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 259: 13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
CTR value at CEVT1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] All capture values valid (can be read) at this time SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 260: Ecap Initialization For Cap Mode Delta Time, Rising Edge Trigger
// Fetch Time-Stamp captured at T2 Period2 = ECAPxRegs.CAP3; // Fetch Time-Stamp captured at T3 Period3 = ECAPxRegs.CAP4; // Fetch Time-Stamp captured at T4 Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 261: 13.3.4 Time Difference (Delta) Operation Rising And Falling Edge Trigger Example
CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CTR value at CEVT1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 262: Ecap Initialization For Cap Mode Delta Time, Rising And Falling Edge Triggers
DutyOffTime2 = ECAPxRegs.CAP1; // Fetch Time-Stamp captured at T1 Period1 = DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2; Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 263: Application Of The Apwm Mode
Figure 13-14. PWM Waveform Details of APWM Mode Operation TSCTR FFFFFFFF 1000h APRD 500h ACMP 300h 0000000C APWMx (o/p pin) Off−time Period time SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 264: Ecap Initialization For Apwm Mode
Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is shown. Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 265: Multichannel Pwm Example Using 4 Ecap Modules
APWM1 (o/p pin) CTR=PRD (SyncOut) Time Phase = 0° Slave APWM(2−4) module/s 10,000 APRD(2) 5,000 APRD(3) 4,000 APRD(4) Time SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 266: Ecap1 Initialization For Multichannel Pwm Generation With Synchronization
CAP1 4000 CTRPHS CTRPHS ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 TSCTRSTOP EC_RUN Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 267 (Legs). Note eCAP1 module is the Master and issues a sync out pulse to the slaves (modules 2, 3) whenever TSCTR = Period value. SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 268: Multiphase (Channel) Interleaved Pwm Example Using 3 Ecap Modules
APWM1 APWM2 APWM3 Vout TSCTR 1200 APRD(1) APRD(1) SYNCO pulse (CTR=PRD) APWM1 Φ2=120° CTRPHS(2)=800 APWM2 Φ3=240° CTRPHS(3)=400 APWM3 Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 269: Ecap1 Initialization For Multichannel Pwm Generation With Phase Control
// Set Duty cycle i.e. compare value = 700 ECAP3Regs.CAP2 = 700; // Set Duty cycle i.e. compare value = 700 SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 270: Registers
Table 13-14. Time-Stamp Counter Register (TSCTR) Field Descriptions Field Value Description 31-0 TSCTR 0-FFFF FFFFh Active 32-bit counter register that is used as the capture time-base Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 271: Counter Phase Control Register (Ctrphs)
• Time-Stamp (i.e., counter value) during a capture event • Software - may be useful for test purposes • APRD active register when used in APWM mode SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 272: Capture 2 Register (Cap2)
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. You update the PWM period value through this register. In this mode, CAP3 shadows CAP1. Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 273: Capture 4 Register (Cap4)
Enable Loading of CAP1-4 registers on a capture event Disable CAP1-4 register loads at capture event time. Enable CAP1-4 register loads at capture event time. SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 274 Capture Event 1 Polarity select Capture Event 1 triggered on a rising edge (RE) Capture Event 1 triggered on a falling edge (FE) Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 275: Ecap Control Register 2 (Ecctl2)
Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event. TSCTRSTOP Time Stamp (TSCTR) Counter Stop (freeze) Control TSCTR stopped TSCTR free-running SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 276: Ecap Interrupt Enable Register (Eceint)
4. Configure peripheral registers 5. Clear spurious eCAP interrupt flags 6. Enable eCAP interrupts 7. Start eCAP counter 8. Enable global interrupts Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 277: Ecap Interrupt Enable Register (Eceint)
Capture Event 1 Interrupt Enable Disable Capture Event 1 as an Interrupt source Enable Capture Event 1 as an Interrupt source Reserved Reserved SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 278: Ecap Interrupt Flag Register (Ecflg)
Indicates the first event occurred at ECAPn pin. Global Interrupt Status Flag Indicates no interrupt generated. Indicates that an interrupt was generated. Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 279: Ecap Interrupt Clear Register (Ecclr)
Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 280: Ecap Interrupt Forcing Register (Ecfrc)
Force Capture Event 1 No effect. Always reads back a 0. Writing a 1 sets the CEVT1 flag bit. Reserved Reserved Enhanced Capture (eCAP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 281: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 13-26. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 44D2 2100h Revision ID. SPRUH91D – March 2013 – Revised September 2016 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 282: Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
........................... Topic Page ..................... 14.1 Introduction ..................... 14.2 Architecture ..............14.3 Applications to Power Topologies ......................14.4 Registers Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 283: Introduction
Each ePWM module consists of seven submodules and is connected within a system via the signals shown in Figure 14-2. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 284: Multiple Epwm Modules
EPWM2A Interrupt GPIO ePWM2 module EPWM2B Controller SYNCO SYNCI EPWMxINT EPWMxA ePWMx module EPWMxB SYNCO Peripheral Frame 1 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 285: Submodules And Signal Connections For An Epwm Module
Figure 14-3 also shows the key internal submodule interconnect signals. Each submodule is described in detail in Section 14.2. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 286: Epwm Submodules And Critical Internal Signal Interconnects
(DB) (PC) (TZ) EPWMB EPWMxB CMPB active (16) EPWMxTZINT CMPB shadow (16) CTR = 0 TZ1 to TZn Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 287: 14.1.3 Register Mapping
These registers are only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved. See your device-specific data manual to determine which instances include the HRPWM. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 288: 14.2 Architecture
• Duty cycle of the second and subsequent pulses. • Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through without modification. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 289 Section 14.2.10 • Enable extended time resolution capabilities (HRPWM) • Configure finer time granularity control or edge positioning SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 290 // = = = = = = = = = = = = = = = = = = = = = = = = = = // CHPEN bit #define CHP_DISABLE #define CHP_ENABLE Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 291: 14.2.2 Proper Interrupt Initialization Procedure
3. Initialize peripheral registers 4. Clear any spurious ePWM flags 5. Enable ePWM interrupts 6. Enable global interrupts SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 292: 14.2.3 Time-Base (Tb) Submodule
Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 293: Time-Base Submodule Signals And Registers
TBCTL[PHSEN] TBCNT Select Counter Active Reg Disable TBPHS TBCTL[SYNCOSEL] Phase Active Reg Clock SYSCLKOUT TBCLK Prescale TBCTL[HSPCLKDIV] TBCTL[CLKDIV] SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 294: Key Time-Base Signals
When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 295: Time-Base Frequency And Period
TBPRD memory address goes directly to the active register. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 296: Time-Base Counter Synchronization Scheme 1
Figure 14-7. Time-Base Counter Synchronization Scheme 1 GPIO MUX EPWM1SYNCI ePWM1 EPWM1SYNCO EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWMxSYNCI ePWMx EPWMxSYNCO Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 297 Figure 14-8 Figure 14-11 show when events are generated and how the time-base responds to an EPWMxSYNCI signal. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 298: Time-Base Up-Count Mode Waveforms
Figure 14-8. Time-Base Up-Count Mode Waveforms TBCNT FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir CTR = 0 CTR = PRD CNT_max Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 299: Time-Base Down-Count Mode Waveforms
FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = 0 CTR = PRD CNT_max SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 300: Time-Base Up-Down Count Waveforms, Tbctl[Phsdir = 1] Count Up On Synchronization Event
FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = 0 CTR = PRD CNT_max Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 301: 14.2.4 Counter-Compare (Cc) Submodule
CTR = PRD CMPCTL[SHDWBFULL] load Compare B Active Reg. CTR = 0 CMPB CMPCTL[SHDWBMODE] Compare B Shadow Reg. CMPCTL[LOADBMODE] SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 302: Counter-Compare Submodule Registers
Time-base counter equal to zero. TBCNT = 0000h Used to load active counter-compare A and B registers from the shadow register Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 303 To best illustrate the operation of the first three modes, the timing diagrams in Figure 14-14 Figure 14- show when events are generated and how the EPWMxSYNCI signal interacts. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 304: Counter-Compare Event Waveforms In Up-Count Mode
TBCNT FFFFh TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0000h EPWMxSYNCI CTR = CMPA CTR = CMPB Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 305: Counter-Compare Events In Up-Down-Count Mode, Tbctl[Phsdir = 0] Count Down On Synchronization Event
TBCNT FFFFh TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0000h EPWMxSYNCI CTR = CMPB CTR = CMPA SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 306: 14.2.5 Action-Qualifier (Aq) Submodule
AQCTLB Action-Qualifier Control Register For Output B (EPWMxB) AQSFRC Action-Qualifier Software Force Register AQCSFRC Action-Qualifier Continuous Software Force Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 307: Action-Qualifier Submodule Inputs And Outputs
Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still trigger interrupts. See the event-trigger submodule description in Section 14.2.9 details. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 308: Possible Action-Qualifier Actions For Epwmxa And Epwmxb Outputs
Figure 14-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs TB Counter equals: Actions force Comp Comp Zero Period Do Nothing Clear Low Set High Toggle Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 309: Action-Qualifier Event Priority For Up-Down-Count Mode
Counter equal to CMPB on down-count (CBD) Counter equal to CMPA on down-count (CAD) 5 (Lowest) Counter equal to period (TBPRD) SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 310: Behavior If Cmpa/Cmpb Is Greater Than The Period
PWM. Modulate the compare value from 0 to TBPRD+1 to achieve 0-100% PWM duty. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 311: Up-Down-Count Mode Symmetrical Waveform
CMPA = 2, 50% Duty Case 3: EPWMxA/EPWMxB CMPA = 1, 75% Duty Case 4: EPWMxA/EPWMxB CMPA = 0, 100% Duty SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 312: Up, Single Edge Asymmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb-Active High
(5) Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCNT wraps from period to 0000h. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 313: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 314: Up, Single Edge Asymmetric Waveform With Independent Modulation On Epwmxa And Epwmxb-Active Low
(5) Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCNT wraps from period to 0000h. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 315: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 316: Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation On Epwmxa
(4) EPWMxB can be used to generate a 50% duty square wave with frequency = 1/2 × ((TBPRD + 1) × TBCLK) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 317: Epwmx Initialization For
Table 14-18. EPWMx Run Time Changes for Figure 14-24 Register Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CMPB EdgePosB SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 318: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Active Low
(3) Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB). (4) Outputs EPWMxA and EPWMxB can drive independent power switches Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 319: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 320: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Complementary
(5) Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module is also available if the more classical edge delay method is required. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 321: Epwmx Initialization For
Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 322: Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low
(5) To change this example to active high, CMPA and CMPB actions need to be inverted (i.e., Set ! Clear and Clear Set). (6) Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 323: Epwmx Initialization For
Table 14-24. EPWMx Run Time Changes for Figure 14-27 Register Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CMPB EdgePosB SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 324: 14.2.6 Dead-Band Generator (Db) Submodule
DBCTL Dead-Band Control Register DBRED Dead-Band Rising Edge Delay Count Register DBFED Dead-Band Falling Edge Delay Count Register Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 325: Configuration Options For The Dead-Band Generator Submodule
EPWMxA in (10-bit counter) Falling edge 0 S3 delay EPWMxB (10-bit counter) DBCTL[IN_MODE] DBCTL[POLSEL] DBCTL[OUT_MODE] EPWMxB in SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 326: Classical Dead-Band Operating Modes
These are classical dead-band modes and assume that DBCTL[IN_MODE] = 0,0. That is, EPWMxA in is the source for both the falling-edge and rising-edge delays. Enhanced, non-traditional modes can be achieved by changing the IN_MODE configuration. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 327: Dead-Band Waveforms For Typical Cases (0% < Duty < 100%)
RED = DBRED × T TBCLK Where T is the period of TBCLK, the prescaled version of SYSCLKOUT. TBCLK SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 328: 14.2.7 Pwm-Chopper (Pc) Submodule
The PWM-chopper submodule operation is controlled via the register in Table 14-27. Table 14-27. PWM-Chopper Submodule Registers Acronym Register Description Address Offset Shadowed PCCTL PWM-chopper Control Register Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 329: Pwm-Chopper Submodule Signals And Registers
Divider and PSCLK [CHPEN] duty control PCCTL [OSHTWTH] PCCTL[CHPFREQ] PCCTL[CHPDUTY] Pulse-width PWMB_ch EPWMxB shot OSHT EPWMxA Start Bypass SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 330: Simple Pwm-Chopper Submodule Waveforms Showing Chopping Action Only
Subsequent Sustaining Pulses Start OSHT pulse EPWMxA in PSCLK Prog. pulse width (OSHTWTH) OSHT EPWMxA out Sustaining pulses Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 331: Pwm-Chopper Submodule Waveforms Showing The Pulse Width (Duty Cycle) Control Of Sustaining Pulses
Sustaining Pulses PSCLK PSCLK period PSCLK Period 62.5% 87.5% 37.5% 12.5% Duty Duty Duty Duty Duty Duty Duty SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 332: 14.2.8 Trip-Zone (Tz) Submodule
Software-forced tripping is also supported. • The trip-zone submodule can be fully bypassed if it is not required. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 333: Trip-Zone Submodule Registers
TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in Table 14-29, can be taken on a trip event. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 334: Possible Actions On A Trip Event
14.2.8.4 Generating Trip Event Interrupts Figure 14-37 Figure 14-38 illustrate the trip-zone submodule control and interrupt logic, respectively. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 335: Trip-Zone Submodule Mode Control Logic
TZEINT[CBC] TZFLG[OST] Generate EPWMxTZINT interrupt Clear TZCLR[OST] (Interrupt controller) pulse when input=1 Latch OSHT trip event TZEINT[OST] SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 336: 14.2.9 Event-Trigger (Et) Submodule
Event-Trigger Selection Register ETPS Event-Trigger Prescale Register ETFLG Event-Trigger Flag Register ETCLR Event-Trigger Clear Register ETFRC Event-Trigger Force Register Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 337: Event-Trigger Submodule Inter-Connectivity To Interrupt Controller
ETPS reg CTRU=CMPB qualifier count CTR = CMPB CTRD=CMPB ETFLG reg clear ETCLR reg CTR_dir count ETFRC reg SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 338 INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 339: Event-Trigger Interrupt Generator
EPWMxINT 2-bit when ETFRC[INT] Counter input = 1 CTR=0 CTR=PRD Inc CNT CTRU=CMPA CTRD=CMPA ETSEL[INT] CTRU=CMPB CTRD=CMPB ETPS[INTPRD] SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 340: 14.2.10 High-Resolution Pwm (Hrpwm) Submodule
(DB) (PC) (TZ) EPWMB EPWMxB CMPB active (16) EPWMxTZINT CMPB shadow (16) TZ1 to TZn CTR = 0 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 341: Resolution Calculations For Conventionally Generated Pwm
Single-phase buck, boost, and flyback • Multi-phase buck, boost, and flyback • Phase-shifted full bridge • Direct modulation of D-Class power amplifiers SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 342: Operating Logic Using Mep
Shadowed TBPHSHR Extension Register for HRPWM Phase CMPAHR Extension Register for HRPWM Duty HRCNFG HRPWM Configuration Register 1040h Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 343: Relationship Between Mep Steps, Pwm Frequency And Resolution
PWM minimum frequency is based on a maximum period value, TBPRD = 65 535. PWM mode is asymmetrical up-count. Resolution in bits is given for the maximum PWM frequency stated. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 344: Required Pwm Waveform For A Requested Duty
For a PWM Period register value of 80 counts, PWM Period = 80 × 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz Assumed MEP step size for the above example = 180 ps Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 345 = 1600h + 180h CMPAHR value = 1780h; CMPAHR value = 1700h, lower 8 bits will be ignored by hardware. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 346: Low % Duty Cycle Range Limitation Example When Pwm Frequency = 1 Mhz
14-48. In this case low percent duty limitation is no longer an issue. Figure 14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz EPWM1A Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 347: 14.3 Applications To Power Topologies
Figure 14-49. Simplified ePWM Module SyncIn Phase reg EPWMxA Φ=0° EPWMxB CTR = 0 CTR=CMPB SyncOut SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 348: 14.3.2 Key Configuration Capabilities
Phase reg SyncIn SyncIn Phase reg Φ=0° EPWM2A Φ=0° EPWM1A EPWM1B EPWM2B CTR=0 CTR=0 CTR=CMPB CTR=CMPB SyncOut SyncOut Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 349: 14.3.3 Controlling Multiple Buck Converters With Independent Frequencies
EPWM4B CTR=0 EPWM4A CTR=CMPB SyncOut NOTE: Θ = X indicates value in phase register is a "don't care" SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 350: Buck Waveforms For (Note: Only Three Bucks Shown Here)
Figure 14-51 (Note: Only three bucks shown here) 1200 EPWM1A 1400 EPWM2A EPWM3A Indicates this event triggers an interrupt Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 351: Epwm1 Initialization For
CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR = 0 LOADBMODE CC_CTR_ZERO Load on CTR = 0 AQCTLA AQ_CLEAR AQ_SET SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 352: 14.3.4 Controlling Multiple Buck Converters With Same Frequencies
Buck #3 Slave Phase reg EPWM2A SyncIn Φ=X EPWM2A EPWM2B Vin4 Vout4 CTR=0 CTR=CMPB Buck #4 SyncOut EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 353: Pwm2 Pwm1
Applications to Power Topologies www.ti.com Figure 14-54. Buck Waveforms for Figure 14-53 (Note: F PWM2 PWM1 EPWM1A EPWM1B EPWM2A EPWM2B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 354: Epwm1 Initialization For
EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 300; // adjust duty for output EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 355: 14.3.5 Controlling Multiple Half H-Bridge (Hhb) Converters
CTR=0 CTR=CMPB EPWM1B SyncOut Slave Phase reg SyncIn DC_bus EPWM2A out2 Φ=0° EPWM2B CTR=0 EPWM2A CTR=CMPB SyncOut EPWM2B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 356: Pwm2 Pwm1
Figure 14-56. Half-H Bridge Waveforms for Figure 14-55 (Note: F PWM2 PWM1 EPWM1A EPWM1B Pulse Center EPWM2A EPWM2B Pulse Center Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 357: Epwm1 Initialization For
EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 250; // adjust duty for output EPWM2B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 358: Controlling Dual 3-Phase Inverters For Motors (Aci And Pmsm)
3 phase motor SyncOut Slave Phase reg SyncIn 3 phase inverter #2 Φ=0° EPWM6A EPWM6B CTR=0 CTR=CMPB SyncOut Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 359: 3-Phase Inverter Waveforms For (Only One Inverter Shown)
Figure 14-58. 3-Phase Inverter Waveforms for Figure 14-57 (Only One Inverter Shown) EPWM1A EPWM1B Φ2=0 EPWM2A EPWM2B Φ3=0 EPWM3A EPWM3B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 360: Epwm1 Initialization For
Enable Dead-band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED FED = 50 TBCLKs DBRED RED = 50 TBCLKs Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 361: Epwm3 Initialization For
EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 362: 14.3.7 Practical Applications Using Phase Control Between Pwm Modules
SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCNT register so the slave time-base is always leading the master's time-base by 120°. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 363: 14.3.8 Controlling A 3-Phase Interleaved Dc/Dc Converter
TBPHS(3,3) = (600/3) × (3 - 1) = 200 × 2 = 400 (Phase value for Slave module 3) Figure 14-62 shows the waveforms for the configuration in Figure 14-61. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 364: Control Of A 3-Phase Interleaved Dc/Dc Converter
SyncIn EPWM2A Φ=120° Φ=120° EPWM2B CTR=0 CTR=CMPB SyncOut Slave Phase reg SyncIn EPWM3A Φ=240° EPWM3B CTR=0 CTR=CMPB SyncOut Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 365: 3-Phase Interleaved Dc/Dc Converter Waveforms For
Figure 14-62. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 14-61 EPWM1A EPWM1B Φ2=120° TBPHS (=300) EPWM2A EPWM2B Φ2=120° TBPHS (=300) EPWM3A EPWM3B SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 366: Epwm1 Initialization For
Enable Dead-band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED FED = 20 TBCLKs DBRED RED = 20 TBCLKs Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 367: Epwm3 Initialization For
EPwm2Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM3A SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 368: 14.3.9 Controlling Zero Voltage Switched Full Bridge (Zvsfb) Converter
EPWM1A EPWM2A SyncOut Slave Phase reg SyncIn EPWM2A Φ=Var° EPWM1B EPWM2B EPWM2B CTR=0 CTR=CMPB SyncOut Var = Variable Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 369: Zvs Full-H Bridge Waveforms
Figure 14-64. ZVS Full-H Bridge Waveforms 1200 EPWM1A ZVS transition Power phase EPWM1B ZVS transition Φ2=variable TBPHS =(1200−Φ2) EPWM2A EPWM2B Power phase SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 370: Epwm1 Initialization For
// Update ZVS transition interval EPwm2Regs.DBFED = FED2_NewValue; // Update ZVS transition interval EPwm2Regs.DBRED = RED2_NewValue; // Update ZVS transition interval Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 371: 14.4 Registers
R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 372: Time-Base Control Register (Tbctl) Field Descriptions
CTR = 0: Time-base counter equal to zero (TBCNT = 0000h) CTR = CMPB : Time-base counter equal to counter-compare B (TBCNT = CMPB) Disable EPWMxSYNCO signal Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 373: Time-Base Status Register (Tbsts)
14.4.1.3 Time-Base Phase Register (TBPHS) The time-base phase register (TBPHS) is shown in Figure 14-67 and described in Table 14-54. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 374: Time-Base Phase Register (Tbphs)
Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 375: 14.4.2 Counter-Compare Submodule Registers
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this location is reserved. See your device-specific data manual to determine which instances include the HRPWM. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 376: Counter-Compare Control Register (Cmpctl)
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD) Load on either CTR = 0 or CTR = PRD Freeze (no loads possible) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 377: Counter-Compare A Register (Cmpa)
• In either mode, the active and shadow registers share the same memory map address. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 378: 14.4.3 Action-Qualifier Submodule Registers
Action-Qualifier Output B Control Register Section 14.4.3.2 AQSFRC Action-Qualifier Software Force Register Section 14.4.3.3 AQCSFRC Action-Qualifier Continuous Software Force Register Section 14.4.3.4 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 379: Action-Qualifier Output A Control Register (Aqctla)
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 380: Action-Qualifier Output B Control Register (Aqctlb)
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 381: Action-Qualifier Software Force Register (Aqsfrc)
Set (high) Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir) SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 382: 14.4.4 Dead-Band Generator Submodule Registers
DBRED Dead-Band Generator Rising Edge Delay Register Section 14.4.4.2 DBFED Dead-Band Generator Falling Edge Delay Register Section 14.4.4.3 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 383: Dead-Band Generator Control Register (Dbctl)
Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE]. SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 384: Dead-Band Generator Rising Edge Delay Register (Dbred)
Table 14-69. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions Bits Name Value Description 15-10 Reserved Reserved 0-3FFh Falling Edge Delay Count. 10-bit counter Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 385: 14.4.5 Pwm-Chopper Submodule Register
4 × SYSCLKOUT/8 wide to 16 × SYSCLKOUT/8 wide CHPEN PWM-chopping Enable Disable (bypass) PWM chopping function Enable chopping function SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 386: 14.4.6 Trip-Zone Submodule Registers
Disable TZn as a CBC trip source for this ePWM module. Enable TZn as a CBC trip source for this ePWM module. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 387: Trip-Zone Control Register (Tzctl)
Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt. Reserved Reserved SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 388: Trip-Zone Flag Register (Tzflg)
This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5). Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 389: Trip-Zone Clear Register (Tzclr)
Writing of 0 is ignored. Always reads back a 0. Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit. Reserved Reserved SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 390: 14.4.7 Event-Trigger Submodule Registers
Enable event: time-base counter equal to CMPB when the timer is incrementing. Enable event: time-base counter equal to CMPB when the timer is decrementing. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 391: Event-Trigger Prescale Register (Etps)
Generate an interrupt on the first event INTCNT = 01 (first event) Generate interrupt on ETPS[INTCNT] = 1,0 (second event) Generate interrupt on ETPS[INTCNT] = 1,1 (third event) SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 392: Event-Trigger Flag Register (Etflg)
Writing a 0 has no effect. Always reads back a 0. Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 393: 14.4.8 High-Resolution Pwm Submodule Registers
Time-Base Phase High-Resolution Register Section 14.4.8.1 CMPAHR Counter-Compare A High-Resolution Register Section 14.4.8.2 1040h HRCNFG HRPWM Configuration Register Section 14.4.8.3 SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 394: Time-Base Phase High-Resolution Register (Tbphshr)
Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h. Reserved Reserved Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 395: Hrpwm Configuration Register (Hrcnfg)
HRPWM capability is disabled (default on reset) MEP control of rising edge MEP control of falling edge MEP control of both edges SPRUH91D – March 2013 – Revised September 2016 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 396: Enhanced Quadrature Encoder Pulse (Eqep) Module
This chapter describes the eQEP..........................Topic Page ..................... 15.1 Introduction ..................... 15.2 Architecture ....................15.3 eQEP Registers Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 397: 15.1 Introduction
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 398: Qep Encoder Output Signal For Forward/Reverse Movement
±0.1T 0.25T QEPI (gated to A and B) ±0.1T 0.5T QEPI (gated to A) ±0.5T QEPI (ungated) Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 399 DSP software switch over to Equation 1 when the motor speed rises above some specified threshold. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 400: 15.2 Architecture
Quadrature edge-capture unit for low-speed measurement (QCAP) • Unit time base for speed/frequency measurement (UTIME) • Watchdog timer for detecting stalls (QWDOG) Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 401: Functional Block Diagram Of The Eqep Peripheral
PCSOUT EQEPxSOUT QPOSILAT EQEPxS EQEPxSOE QPOSCNT QEINT QPOSCMP QPOSINIT QFRC QPOSMAX QCLR QPOSCTL Enhanced QEP (eQEP) peripheral SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 402: Quadrature Decoder Unit (Qdu)
QDECCTL:XCR QDECCTL:QIP QDECCTL:QSRC EQEPxIIN QDECCTL:IGATE EQEPxSIN QDECCTL:QSP QDECCTL:SPSEL EQEPxIOUT PCSOUT EQEPxSOUT QDECCTL:SPSEL EQEPxIOE QDECCTL:SOEN EQEPxSOE Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 403: Quadrature Decoder Truth Table
Decrement QB↓ TOGGLE Increment or Decrement QB↓ QA↓ DOWN Increment QA↑ Decrement QB↑ TOGGLE Increment or Decrement SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 404: Quadrature Decoder State Machine
QPOSCNT −1 −1 −1 −1 −1 −1 −1 +1 +1 +1 +1 +1 +1 −1 −1 −1 Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 405: Position Counter And Control Unit (Pccu)
Position Counter Reset on the first Index Event • Position Counter Reset on Unit Time Out Event (Frequency Measurement) SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 406: Position Counter Reset By Index Pulse For 1000 Line Encoder (Qposmax = 3999 Or F9Fh)
Figure 15-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) QCLK QEPSTS:QDF QPOSCNT F9C Index interrupt/ index event marker QPOSILAT QEPSTS:QDLF Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 407: Position Counter Underflow/Overflow (Qposmax = 4)
(QEPCTL[IEL]=11). Figure 15-9. Position Counter Underflow/Overflow (QPOSMAX = 4) QCLK QDIR QPOSCNT OV/UF QCLK QDIR QPOSCNT OV/UF SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 408 (QEPCTL[IEL] = 11). Figure 15-10 shows the position counter latch using an index event marker. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 409: Software Index Marker For 1000-Line Encoder (Qepctl[Iel] = 1)
Figure 15-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) QCLK QEPSTS:QDF QPOSCNT Index interrupt/ index event marker QPOSILAT QEPSTS:QDLF SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 410: Strobe Event Latch (Qepctl[Sel] = 1)
The strobe event latch interrupt flag (QFLG[SEL]) is set when the position counter is latched to the QPOSSLAT register. Figure 15-11. Strobe Event Latch (QEPCTL[SEL] = 1) QCLK QEPST:QDF QPOSCNT QIPOSSLAT Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 411: Eqep Position-Compare Unit
(QFLG[PCR]) interrupt after loading. • Load on compare match • Load on position-counter zero event SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 412: Eqep Position-Compare Event Generation Points
Figure 15-14. eQEP Position-compare Sync Output Pulse Stretcher QPOSCMP QPOSCNT PCEVNT PCSPW PCSPW PCSPW PCSOUT (active HIGH) Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 413: 15.2.5 Eqep Edge Capture Unit
The QCAPCTL register should not be modified dynamically (such as switching CAPCLK prescaling mode from QCLK/4 to QCLK/8). The capture unit must be disabled before changing the prescaler. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 414: Eqep Edge Capture Unit
Figure 15-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) QCLK UPEVNT X=N x P N - Number of quadrature periods selected using QCAPCTL[UPPS] bits Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 415: Eqep Edge Capture Unit - Timing Details
Unit time (T) and unit period (X) are configured using the QUPRD and QCAPCTL[UPPS] registers. Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT registers. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 416: 15.2.6 Eqep Watchdog
(QWDPRD). Figure 15-18. eQEP Watchdog Timer QWDOG QEPCTL:WDE SYSCLKOUT SYSCLKOUT QWDTMR QCLK RESET WDTOUT QWDPRD QFLG:WTO Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 417: 15.2.7 Unit Timer Base
You can force an interrupt event by way of the interrupt force register (QFRC), which is useful for test purposes. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 418: 15.3 Eqep Registers
Section 15.3.23 QCPRDLAT eQEP Capture Period Latch Register Section 15.3.24 REVID eQEP Revision ID Register Section 15.3.25 Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 419: Eqep Position Counter Register (Qposcnt)
Table 15-5. eQEP Maximum Position Count Register (QPOSMAX) Field Descriptions Bits Name Value Description 31-0 QPOSMAX 0-FFFF FFFFh This register contains the maximum position counter value. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 420: Eqep Position-Compare Register (Qposcmp)
The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 421: Eqep Position Counter Latch Register (Qposlat)
This register contains the period count for unit timer to generate periodic unit time events to latch the eQEP position information at periodic interval and optionally to generate interrupt. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 422: Eqep Watchdog Timer Register (Qwdtmr)
This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value, a watchdog timeout interrupt is generated. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 423: Qep Decoder Control Register (Qdecctl)
QEPS input polarity No effect Negates QEPS input Reserved Always write as 0 15.3.13 eQEP Control Register (QEPCTL) SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 424: Eqep Control Register (Qepctl)
Software initialization of position counter Do nothing (action disabled) Initialize position counter, this bit is cleared automatically Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 425 Disable eQEP unit timer Enable unit timer eQEP watchdog enable Disable the eQEP watchdog timer Enable the eQEP watchdog timer SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 426: Eqep Capture Control Register (Qcapctl)
UPEVNT = QCLK/128 UPEVNT = QCLK/256 UPEVNT = QCLK/512 UPEVNT = QCLK/1024 UPEVNT = QCLK/2048 Ch-Fh Reserved Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 427: Eqep Position-Compare Control Register (Qposctl)
2 × 4 × SYSCLKOUT cycles 2h-FFFh 3 × 4 × SYSCLKOUT cycles to 4096 × 4 × SYSCLKOUT cycles SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 428: Eqep Interrupt Enable Register (Qeint)
Interrupt is disabled Interrupt is enabled Position counter error interrupt enable Interrupt is disabled Interrupt is enabled Reserved Reserved Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 429: Eqep Interrupt Flag Register (Qflg)
Set on simultaneous transition of QEPA and QEPB Position counter error interrupt flag No interrupt generated Position counter error SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 430: Eqep Interrupt Clear Register (Qclr)
No effect Clears the interrupt flag Clear quadrature direction change interrupt flag No effect Clears the interrupt flag Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 431 Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1. SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 432: Eqep Interrupt Force Register (Qfrc)
Force the interrupt Force position counter error interrupt No effect Force the interrupt Reserved Always write as 0 Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 433: Eqep Status Register (Qepsts)
Position counter error flag. This bit is not sticky and it is updated for every index event. No error occurred during the last index transition. Position counter error SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 434: Eqep Capture Timer Register (Qctmr)
0-FFFFh The eQEP capture timer value can be latched into this register on two events viz., unit timeout event, reading the eQEP position counter. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 435: Eqep Capture Period Latch Register (Qcprdlat)
Table 15-27. eQEP Revision ID Register (REVID) Field Descriptions Bits Name Value Description 31-0 44D3 1103h eQEP revision ID SPRUH91D – March 2013 – Revised September 2016 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 436: Spruh91D - March 2013 - Revised September 2016
Architecture .................... 16.3 Transfer Examples ......................16.4 Registers ........................ 16.5 Tips ..................16.6 Setting Up a Transfer Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 437: 16.1 Introduction
– Error and status recording to facilitate debug – Missed event detection • 128 parameter RAM (PaRAM) entries • 4 shadow regions SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 438 16-, 32-, or 64-bytes burst size. See the Chip Configuration 0 Register (CFGCHIP0) in the System Configuration (SYSCFG) Module chapter for details to change the default burst size value. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 439: 16.1.3 Functional Block Diagram
Transfer controllers are the transfer engine for the EDMA3. Performs the controller(s) read/writes as dictated by the transfer requests submitted by the EDMA3CC. (EDMA3TC) SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 440 QDMA channel n mapping register (QCHMAPn) and can point to any PaRAM set entry. TR synchronization See Trigger event. (sync) event Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 441: 16.2 Architecture
DMA channels being higher priority than the QDMA channels. Among the two groups of channels, the lowest-numbered channel is the highest priority. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 442: Edma3 Channel Controller (Edma3Cc) Block Diagram
(like missed events, exceeding event queue thresholds, etc.). For more details on error interrupts, see Section 16.2.9.4. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 443: Edma3 Transfer Controller (Edma3Tc) Block Diagram
For details on command fragmentation and optimization, see Section 16.2.11.1.2. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 444: 16.2.2 Types Of Edma3 Transfers
CCNT frames in Block/3rd dimmension Frame CCNT Array 1 Array 2 Array BCNT BCNT arrays in Frame/2nd dimmension Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 445: A-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
CIDX (SRC|DST) (SRC|DST) (SRC|DST) BIDX BIDX BIDX Frame 2 Array 0 Array 1 Array 2 Array 3 SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 446: Ab-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
NOTE: ABC-synchronized transfers are not directly supported. But can be logically achieved by chaining between multiple AB-synchronized transfers. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 447: Parameter Ram (Param)
Parameter set n Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 448: Edma3 Channel Parameter Description
32-bit accesses on the parameter RAM for best code compatibility. For example, switching the endianness of the processor swaps addresses of the 16-bit fields, but 32-bit accesses avoid the issue entirely. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 449 For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 450 You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM address that falls in the range of the available PaRAM addresses on the device. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 451: Dummy And Null Transfer Request
A link update occurs when the PaRAM set is exhausted, as described in Section 16.2.3.7. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 452: Parameter Updates In Edma3Cc (For Non-Null, Non-Dummy Param Set)
You should ensure that no transfer is allowed to cross internal port boundaries between peripherals. A single TR must target a single source/destination slave endpoint. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 453 8 PaRAM words are updated before the new QDMA event can trigger the transfer for that PaRAM entry. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 454 ACNT = 2 (2 bytes) and BCNT = 256. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 455: Linked Transfer Example
Parameter set 2 01C0 4060h Parameter set 3 Link=FFFFh 01C0 4FC0h Parameter set 126 1CA0 4FE0h Parameter set 127 SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 456: Link-To-Self Transfer Example
01C0 4FC0h Parameter set 126 DSTCIDX X SRCCIDX X 1CA0 4FE0h Parameter set 127 Rsvd CCNT X Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 457: 16.2.4 Initiating A Dma Transfer
For the synchronization events associated with each of the programmable DMA channels, see your device-specific data manual to determine the event to channel mapping. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 458 NOTE: Chained event registers, event registers, and event set registers operate independently. An event (En) can be triggered by any of the trigger sources (event-triggered, manually- triggered, or chain-triggered). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 459 QDMA event and initiate another set of transfers as specified by the linked set. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 460: 16.2.5 Completion Of A Dma Transfer
There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal completion, early completion, and dummy/null completion. This applies to both chained events and completion interrupt generation. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 461: 16.2.6 Event, Channel, And Param Mapping
(unused), that channel can be used for manually-triggered or chained-triggered transfers, for linking/reloading, or as a QDMA channel. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 462: Edma3 Dma Channel To Param Mapping
Reload/QDMA PaRAM Set n - 2 Reload/QDMA PaRAM Set n - 1 Reload/QDMA PaRAM Set n Reload/QDMA Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 463: Qdma Channel To Param Mapping
Parameter set n Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 464: 16.2.7 Edma3 Channel Controller Regions
Table 16-6. Shadow Region Registers DRAEm QRAEm QEER QEECR QEESR EECR EESR SECR IECR IESR Register not affected by DRAE IEVAL Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 465: Shadow Region Registers
DRAE/QRAE registers. If exclusive access to any given channel/TCC code is required for a region, then only that region's DRAE/QRAE should have the associated bit set. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 466: 16.2.8 Chaining Edma3 Channels
5 (All TRs) 16.2.9 EDMA3 Interrupts The EDMA3 interrupts are divided into 2 categories: • Transfer completion interrupts Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 467: Transfer Complete Code (Tcc) To Edma3Cc Interrupt Mapping
IPR2 00 0011b IPR3 00 0100b IPR4 … … … … 01 1110b IPR30 01 1111b IPR31 SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 468: Number Of Interrupts
IER.En & DRAE1.En) where n is the number of shadow regions supported in the EDMA3CC for a specific device. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 469: Interrupt Diagram
SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 471 NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the IEVAL operated upon is from that particular shadow region memory map. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 472: Error Interrupt Operation
EDMA3_CC0_ERRINT Note: n is the number of queues supported in the EDMA3CC for a specific device. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 473: Event Queue(S)
EDMA3TC. In this case, the event is not logged in the event queue status registers. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 474 (CCERR) and the THRXCD bit in QSTATn, where n stands for the event queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 475: Edma3 Transfer Controller (Edma3Tc)
DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the source/destination addresses. Each BCNT number of arrays are then serviced in succession. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 476 TR0), the transfer controller issues that the write commands are issued in order (that is, write commands for TR0 will be issued before write commands for TR1). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 477 FIFO register entry 3 and the second pending TR is read from the destination FIFO register entry 0. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 478: 16.2.12 Event Dataflow
10. This continues until the TR completes and on receiving the acknowledgement signal from the destination slave end point, the EDMA3TCn then signals completion status to the EDMA3CC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 479: 16.2.13 Edma3 Prioritization
(QER) QDMA trigger Completion detection From EDMA3TC(s) Error Completion detection interrupt EDMA3 channel controller EDMA3CC_ERRINT EDMA3CC_INT[1:0] SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 480 EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 481: 16.2.14 Edma3Cc And Edma3Tc Performance And System Considerations
TC will end up issuing several ACNT byte (4 byte) size commands to complete the transfers, which will result in inefficient usage of the read/write buses. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 482: Edma3 Operating Frequency (Clock Control)
DMA channel associated with the peripheral (clearing the EER bit for the channel), then disable the EDMA3CC, and finally disable the EDMA3TC(s). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 483: 16.2.18 Emulation Considerations
1180 0000h 245 246 247 248 245 246 247 249 250 251 252 253 254 253 254 255 SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 484: Block Move Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 485: 16.3.2 Subframe Extraction Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 486: 16.3.3 Data Sorting Example
C_1023 C_1024 D_1022 D_1023 D_1024 A_1022 B_1022 C_1022 D_1022 A_1023 B_1023 C_1023 D_1023 A_1024 B_1024 C_1024 D_1024 Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 487: Data Sorting Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 488: 16.3.4 Peripheral Servicing Example
0. Figure 16-21. Servicing Incoming McBSP Data Example 1180 0000h REVT 01D0 0000h Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 489: Servicing Incoming Mcbsp Data Example Param
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 490: Servicing Peripheral Burst Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 491: Servicing Continuous Mcbsp Data Example
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 01D0 0004h A9i A10i A11i A12i A13i 1180 1080h B7o B8o B9o B10o B11o B12o B13o SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 492: Servicing Continuous Mcbsp Data Example Param
Figure 16-27. Servicing Continuous McBSP Data Example Reload PaRAM (a) EDMA Reload Parameters (PaRAM Set 64) for Receive Channel Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 493 (d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65) 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0001 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 494 The only differences are the link address provided and the address of the data buffer. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 495: Ping-Pong Buffering For Mcbsp Data Example
1180 1080h 1180 1880h B9o B10o B11o B12o B13o B9o B10o B11o B12o B13o A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 01D0 0004h SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 496: Ping-Pong Buffering For Mcbsp Example Param
Figure 16-30. Ping-Pong Buffering for McBSP Example Pong PaRAM (a) EDMA Pong Parameters for Channel 3 at Set 64 Linked to Set 65 Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 497: Ping-Pong Buffering For Mcbsp Example Ping Param
0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 498 Figure 16-34 shows the EDMA3 setup and illustration of the broken up smaller packet transfers. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 499: Intermediate Transfer Completion Chaining Example
BCNT = 1 CCNT = 1 1D transfer of 16 KByte elements OPT.ITCINTEN = 0 OPT.TCC = Don’t care SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 500: 16.4 Registers
Link Address/B Count Reload Section 16.4.1.6 SRC_DST_CIDX Source C Index/Destination C Index Section 16.4.1.7 CCNT C Count Section 16.4.1.8 Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 501: Channel Options Parameter (Opt)
CPU, the corresponding IER[TCC] bit must be set to 1. Reserved Reserved. Always write 0 to this bit. Reserved Reserved SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 502 (INCR) mode (SAM/DAM = 0) by appropriately programming the count and indices values. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 503: Channel Source Address Parameter (Src)
0-FFFFh A count for 1st Dimension. Unsigned value specifying the number of contiguous bytes within an array (first dimension of the transfer). Valid values range from 1 to 65 535. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 504: Channel Destination Address Parameter (Dst)
Source B index. Signed value specifying the byte address offset between source arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 505: Link Address/B Count Reload Parameter (Link_Bcntrld)
PaRAM set. The 5 LSBs of the LINK field should be cleared to 0. A value of FFFFh specifies a null link. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 506: Source C Index/Destination C Index Parameter (Src_Dst_Cidx)
C counter. Unsigned value specifying the number of frames in a block, where a frame is BCNT arrays of ACNT bytes. Valid values range from 1 to 65 535. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 507: 16.4.2 Edma3 Channel Controller (Edma3Cc) Registers
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 508 QDMA Event Enable Set Register — 2090h QSER QDMA Secondary Event Register — 2094h QSECR QDMA Secondary Event Clear Register — Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 509 QDMA Secondary Event Register — 2294h QSECR QDMA Secondary Event Clear Register — 4000h-4FFFh — Parameter RAM (PaRAM) — SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 510: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 511: Edma3Cc Configuration Register (Cccfg) Field Descriptions
5h-7h Reserved Reserved Reserved NUM_DMACH 0-7h Number of DMA channels. 0-3h Reserved 32 DMA channels 5h-7h Reserved SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 512: Qdma Channel N Mapping Register (Qchmapn)
Points to the specific PaRAM entry or the trigger word in the PaRAM set pointed to by PAENTRY. A write to the trigger word results in a QDMA event being recognized. Reserved Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 513: Dma Channel Queue Number Register N (Dmaqnumn)
Event n is queued on Q1. 2h-7h Reserved Table 16-25. Bits in DMAQNUMn DMAQNUMn En bit 8-10 12-14 16-18 20-22 24-26 28-30 SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 514: Qdma Channel Queue Number Register (Qdmaqnum)
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 515: Event Missed Register (Emr)
Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear register (EMCR). No missed event. Missed event occurred. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 516: Event Missed Clear Register (Emcr)
No effect. Corresponding missed event bit in the event missed register (EMR) is cleared (En = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 517: Qdma Event Missed Register (Qemr)
Channel 0-7 QDMA event missed. En is cleared by writing a 1 to the corresponding bit in the QDMA event missed clear register (QEMCR). No missed event. Missed event occurred. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 518: Qdma Event Missed Clear Register (Qemcr)
No effect. Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 519: Edma3Cc Error Register (Ccerr)
Queue threshold error for queue 0. QTHRXCD0 is cleared by writing a 1 to the corresponding bit in the EDMA3CC error clear register (CCERRCLR). Watermark/threshold has not been exceeded. Watermark/threshold has been exceeded. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 520: Edma3Cc Error Clear Register (Ccerrclr)
Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in the queue status register 0 (QSTAT0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 521: Error Evaluate Register (Eeval)
EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers (EMR, QEMR, or CCERR). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 522: Dma Region Access Enable Register For Region M (Draem)
Enabled interrupt bits for bit n contribute to the generation of a transfer completion interrupt for shadow region m. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 523: Qdma Region Access Enable For Region M (Qraem)
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return the value from bit n and writes modify the state of bit n. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 524: Event Queue Entry Registers (Qxey)
Event entry y in queue x. Event number: 0-7h QDMA channel number (0 to 7) 0-1Fh DMA channel/event number (0 to 31) Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 525: Queue N Status Register (Qstatn)
Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal values are 0 (0th entry) to Fh (15th entry). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 526: Queue Watermark Threshold A Register (Qwmthra)
Q0. 0-10h The default is 16 (maximum allowed). Disables the threshold errors. 12h-1Fh Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 527: Edma3Cc Status Register (Ccstat)
TRACTV Transfer request active. Transfer request processing/submission logic is inactive. Transfer request processing/submission logic is active. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 528 No enabled DMA events are active within the EDMA3CC. At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 529: Event Register (Er)
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 530: Event Clear Register (Ecr)
(ER). A write of 0 has no effect. No effect. EDMA3CC event is cleared in the event register (ER). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 531: Event Set Register (Esr)
No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 532: Chained Event Register (Cer)
No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 533: Event Enable Register (Eer)
Event is enabled. An external event latched in the event register (ER) is evaluated by the EDMA3CC. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 534: Event Enable Clear Register (Eecr)
No effect. Event is enabled. Corresponding bit in the event enable register (EER) is set (En = 1). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 535: Secondary Event Register (Ser)
Secondary event clear register No effect. Corresponding bit in the secondary event register (SER) is cleared (En = 0). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 536: Interrupt Enable Register (Ier)
Table 16-49. Interrupt Enable Register (IER) Field Descriptions Field Value Description 31-0 Interrupt enable for channels 0-31. Interrupt is not enabled. Interrupt is enabled. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 537: Interrupt Enable Clear Register (Iecr)
Interrupt enable set for channels 0-31. No effect. Corresponding bit in the interrupt enable register (IER) is set (In = 1). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 538: Interrupt Pending Register (Ipr)
Interrupt transfer completion code is not detected or was cleared. Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 539: Interrupt Clear Register (Icr)
Interrupt clear register for TCC = 0-31. No effect. Corresponding bit in the interrupt pending register (IPR) is cleared (In = 0). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 540: Interrupt Evaluate Register (Ieval)
For example, writing to the EVAL bit in IEVAL0 pulses the region 0 completion interrupt, but writing to the EVAL bit in IEVAL1 pulses the region 1 completion interrupt. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 541: Qdma Event Register (Qer)
No effect. Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 542: Qdma Event Enable Register (Qeer)
QDMA channel n is enabled. QDMA events will be recognized and will get latched in the QDMA event register (QER). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 543: Qdma Event Enable Clear Register (Qeecr)
QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 544: Qdma Secondary Event Register (Qser)
QDMA event is not currently stored in the event queue. QDMA event is currently stored in event queue. EDMA3CC will not prioritize additional events. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 545: Qdma Secondary Event Clear Register (Qsecr)
Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER) is cleared (En = 0). SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 546: 16.4.3 Edma3 Transfer Controller (Edma3Tc) Registers
Destination FIFO Source Address Register 3 Section 16.4.3.6.14 3C8h DFCNT3 Destination FIFO Count Register 3 Section 16.4.3.6.15 Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 547: Revision Id Register (Revid)
Description 31-0 Peripheral identifier. 4000 3B00h Uniquely identifies the EDMA3TC and the specific revision of the EDMA3TC. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 548: Edma3Tc Configuration Register (Tccfg)
0-7h FIFO size. 32-byte FIFO 64-byte FIFO 128-byte FIFO (for EDMA3TC0 and EDMA3TC1) 256-byte FIFO 4h-7h Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 549: Edma3Tc Channel Status Register (Tcstat)
Program register set busy. Program set idle and is available for programming by the EDMA3CC. Program set busy. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 550: Error Status Register (Errstat)
EDMA3TC has detected an error at source or destination address. Error information can be read from the error details register (ERRDET). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 551: Error Enable Register (Erren)
Interrupt enable for bus error (BUSERR). BUSERR is disabled. BUSERR is enabled and contributes to the state of EDMA3TC error interrupt generation. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 552: Error Clear Register (Errclr)
Clears the BUSERR bit in the error status register (ERRSTAT) and clears the error details register (ERRDET). Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 553: Error Details Register (Errdet)
Write addressing error Write privilege error Write timeout error Write data error Dh-Eh Reserved Write exclusive operation error SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 554: Error Interrupt Command Register (Errcmd)
EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set to 1. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 555: Read Command Rate Register (Rdrate)
8 EDMA3TC cycles between reads. 16 EDMA3TC cycles between reads. 32 EDMA3TC cycles between reads. 5h-7h Reserved SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 556: Source Active Options Register (Saopt)
Priority 0 - Highest priority 1h-6h Priority 1 to priority 6 Priority 7 - Lowest priority Reserved Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 557: Source Active Source Address Register (Sasrc)
Read command appropriately. Represents the amount of data remaining to be Read. It should be 0 when transfer request (TR) is complete. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 558: Source Active Destination Address Register (Sadst)
B-Index offset between source arrays. Represents the offset in bytes between the starting address of each source array. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 559: Source Active Memory Protection Proxy Register (Sampprxy)
For any other master that sets up the PaRAM entry. If DSP sets up the PaRAM entry. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 560: Source Active Count Reload Register (Sacntrld)
31-0 SADDRBREF 0-FFFF FFFFh Source address B-reference. Represents the starting address for the array currently being Read. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 561: Source Active Destination Address B-Reference Register (Sadstbref)
A-count reload value. Represents the originally programmed value of ACNT. The reload value is used to reinitialize ACNT after each array is serviced. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 562: Destination Fifo Set Source Address B-Reference Register (Dfsrcbref)
Destination address reference for the destination FIFO register set. Represents the starting address for the array currently being written. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 563: Destination Fifo Options Register N (Dfoptn)
Increment (INCR) mode. Source addressing within an array increments. Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching FIFO width. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 564: Destination Fifo Source Address Register N (Dfsrcn)
0-FFFFh A-dimension count. Number of bytes to be transferred in first dimension count/count remaining for destination register set. Represents the amount of data remaining to be written. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 565: Destination Fifo Destination Address Register N (Dfdstn)
B-Index offset between source arrays. Represents the offset in bytes between the starting address of each source array. Always Read as 0. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 566: Destination Fifo Memory Protection Proxy Register N (Dfmpprxyn)
For any other master that sets up the PaRAM entry If DSP sets up the PaRAM entry Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 567: 16.5 Tips
31), make sure that DRAE.E31 is also set for a shadow region completion interrupt because the interrupt pending register bit set will be IPR.I31. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 568: 16.5.2 Miscellaneous Programming/Debug Tips
EDMA3CC and EDMA3TC. The EDMA3CC status register (CCSTAT) and the EDMA3TC channel status register (TCSTAT) should be used. Enhanced Direct Memory Access (EDMA3) Controller SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 569: 16.6 Setting Up A Transfer
ICR before the next set of transfers is performed for the same transfer completion code values. SPRUH91D – March 2013 – Revised September 2016 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 570: Emac/Mdio Module
(PHY) device Management Data Input/Output (MDIO) module integrated in the device..........................Topic Page ..................... 17.1 Introduction ..................... 17.2 Architecture ......................17.3 Registers EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 571: 17.1 Introduction
Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 572: 17.1.3 Functional Block Diagram
8K CPPI DMA Bus Master Interrupt Interrupts Combiner Register Bus EMAC MDIO Interrupts Interrupts EMAC MDIO Module Module MII/RMII Bus MDIO Bus EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 573: 17.1.4 Industry Standard(S) Compliance Statement
(also known as a switch) with a dedicated LAN connecting each bridge port to a single device. Full-duplex operation constitutes a proper subset of the MAC functionality required for half-duplex operation. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 574: 17.2 Architecture
MII_RXCLK pins or to the RMII reference clock pin. Data is transmitted and received with respect to the reference clocks of the interface pins. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 575: 17.2.2 Memory Map
2.5 MHz MII_TXEN 25 MHz MII_COL MII_CRS Physical System layer MII_RXCLK Transformer core device MII_RXD[3−0] (PHY) MII_RXDV MII_RXER RJ−45 MDIO_CLK MDIO_D SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 576: Emac And Mdio Signals For Mii Interface
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 577: Ethernet Configuration-Rmii Connections
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 578: 17.2.4 Ethernet Protocol Overview
60 to 1514 bytes of the packet data. Note that this 4-byte field may or may not be included as part of the packet data, depending on how the EMAC is configured. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 579: 17.2.5 Programming Interface
Figure 17-5. Basic Descriptor Format Bit Fields Word Offset 16 15 Next Descriptor Pointer Buffer Pointer Buffer Offset Buffer Length Flags Packet Length SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 580: Typical Descriptor Linked List
Packet B Fragment 3 500 bytes −−− pNext (NULL) pBuffer Packet C 1514 1514 bytes SOP | EOP 1514 EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 581 HDP that started the process. This process applies when adding packets to a transmit list, and empty buffers to a receive list. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 582 32-bit boundary that describes a packet or a packet fragment. Example 17-1 shows the transmit buffer descriptor described by a C structure. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 583: Transmit Buffer Descriptor Format
/* Packet Flags */ #define EMAC_DSC_FLAG_SOP 0x80000000u #define EMAC_DSC_FLAG_EOP 0x40000000u #define EMAC_DSC_FLAG_OWNER 0x20000000u #define EMAC_DSC_FLAG_EOQ 0x10000000u #define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u #define EMAC_DSC_FLAG_PASSCRC 0x04000000u SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 584 EOP flag. This bit is set by the software application and is not altered by the EMAC. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 585 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 586: Receive Buffer Descriptor Format
Buffer Offset Buffer Length Word 3 OWNER TDOWNCMPLT PASSCRC JABBER OVERSIZE FRAGMENT UNDERSIZED CONTROL OVERRUN CODEERROR ALIGNERROR CRCERROR NOMATCH Packet Length EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 587 The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest value of buffer length for all descriptors in the list. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 588 This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 589 RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 590: 17.2.6 Emac Control Module
To arbitrate between the CPU and EMAC buses for access to internal descriptor memory. • To arbitrate between internal EMAC buses for access to system memory. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 591: 17.2.7 Mdio Module
• MDIO clock generator • Global PHY detection and link state monitoring • Active PHY monitoring • PHY register user access SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 592: Mdio Module Block Diagram
The user access registers USERACCESSn allows the software to submit the access requests for the PHY connected to the device. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 593 USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 594 (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 595 CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr) CSL_FMK(MDIO_USERACCESS0_DATA, data) #define PHYREG_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ) #define PHYREG_waitResults( results ) { while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ); results = CSL_FEXT(MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_DATA); } SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 596: 17.2.8 Emac Module
The receive FIFO consists of three cells of 64-bytes each and associated control logic. The FIFO buffers receive data in preparation for writing into packet buffers in device memory. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 597 MAC transmitter then initiates the packet transmission. The SYNC block transmits the packet over the MII or RMII interfaces in accordance with the 802.3 protocol. Transmit statistics are counted by the statistics block. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 598: 17.2.9 Mac Interface
(in the following order): 1. An Interpacket Gap (IPG). 2. A 7-byte preamble (all bytes 55h). 3. A 1-byte start of frame delimiter (5Dh). EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 599 00.00h. • Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames). SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 600 MII_TXEN is deasserted, then 96 bit times (approximately, but not less) is measured from MII_CRS. 17.2.9.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 601 The MAC operates at 10 Mbps or 100 Mbps, in half-duplex or full-duplex mode, and with or without pause frame support as configured by the host. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 602: 17.2.10 Packet Receive Operation
(MACADDRLO). Since all eight MAC addresses share the upper 40 bits of address, MACADDRHI needs to be written only the first time (for the first channel configured). EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 603 The read value is FFFF FFFCh, if the interrupt was due to a teardown command. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 604 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length inclusive and contain no code, align, or CRC errors. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 605: Receive Frame Treatment Summary
No undersized/fragment frames are transferred. All address matching frames with and without errors transferred to the address match channel SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 606: Middle Of Frame Overrun Treatment
OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 607: 17.2.11 Packet Transmit Operation
(TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 608: 17.2.12 Receive And Transmit Latency
5.12 μs. • Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μs. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 609: 17.2.14 Reset Considerations
MAC status register (MACSTATUS) that gives information about the type of software error that needs to be corrected. For detailed information on error interrupts, see Section 17.2.16.1.4. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 610: 17.2.15 Initialization
Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling. For more information on PHY control registers, see your PHY device documentation. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 611 TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL. 17. Enable the device interrupt in EMAC control module registers CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 612: 17.2.16 Interrupt Support
(RXINTMASKCLEAR). The raw and masked receive interrupt status may be read by reading the receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED), respectively. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 613 Ownership bit not set in SOP buffer • Zero next buffer descriptor pointer with EOP • Zero buffer pointer • Zero buffer length • Packet length error SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 614 The application software must acknowledge the EMAC control module after receiving MDIO interrupts by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 17.3.3.12 for the acknowledge key values. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 615 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT0, and USERINT0. For more details on the interrupt mapping, see the DSP Subsystem chapter . SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 616: 17.2.17 Power Management
SOFT and FREE bits affect the operation of the emulation suspend. NOTE: Emulation suspend has not been tested. Table 17-7. Emulation Control SOFT FREE Description Normal operation Emulation suspend Normal operation EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 617: 17.3 Registers
EMAC Control Module Interrupt Core 2 Receive Threshold Section 17.3.1.8 Interrupt Status Register C2RXSTAT EMAC Control Module Interrupt Core 2 Receive Interrupt Section 17.3.1.9 Status Register SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 618: Emac Control Module Revision Id Register (Revid)
Table 17-9. EMAC Control Module Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Identifies the EMAC Control Module revision. 4EC8 0100h Current revision of the EMAC Control Module. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 619: Emac Control Module Software Reset Register (Softreset)
Software reset bit for the EMAC Control Module. Clears the interrupt status, control registers, and CPPI Ram on the clock cycle following a write of 1. No software reset. Perform a software reset. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 620: Emac Control Module Interrupt Control Register (Intcontrol)
Number of internal EMAC module reference clock periods within a 4 μs time window (see your device-specific data manual for information). EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 621: Emac Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (Cnrxthreshen)
Enable CnRXTHRESHPULSE interrupt generation for RX Channel 0 CnRXTHRESHPULSE generation is disabled for RX Channel 0. CnRXTHRESHPULSE generation is enabled for RX Channel 0. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 622: Emac Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (Cnrxen)
Enable CnRXPULSE interrupt generation for RX Channel 0 CnRXPULSE generation is disabled for RX Channel 0. CnRXPULSE generation is enabled for RX Channel 0. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 623: Emac Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (Cntxen)
Enable CnTXPULSE interrupt generation for TX Channel 0 CnTXPULSE generation is disabled for TX Channel 0. CnTXPULSE generation is enabled for TX Channel 0. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 624: Emac Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (Cnmiscen)
Enable CnMISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding to USERACCESS0) are generated CnMISCPULSE generation is disabled for MDIO USERINT0. CnMISCPULSE generation is enabled for MDIO USERINT0. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 625: Emac Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (Cnrxthreshstat)
RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 626: Emac Control Module Interrupt Core 0-2 Receive Interrupt Status Register (Cnrxstat)
RX Channel 0 does not satisfy conditions to generate a CnRXPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXPULSE interrupt. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 627: Emac Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)
TX Channel 0 does not satisfy conditions to generate a CnTXPULSE interrupt. TX Channel 0 satisfies conditions to generate a CnTXPULSE interrupt. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 628: Emac Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (Cnmiscstat)
Interrupt status for MDIO USERINT0 masked by the CnMISCEN register MDIO USERINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt. MDIO USERINT0 satisfies conditions to generate a CnMISCPULSE interrupt. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 629: Emac Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (Cnrximax)
> 0.5*RXIMAX) pace_counter = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 630: Emac Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (Cntximax)
> 0.5*TXIMAX) pace_counter = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 631: 17.3.2 Mdio Registers
Table 17-23. MDIO Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Identifies the MDIO Module revision. 0007 0104h Current revision of the MDIO Module. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 632: Mdio Control Register (Control)
MDIO_CLK. MDIO_CLK is disabled when CLKDIV is cleared to 0. MDIO_CLK frequency = peripheral clock frequency/(CLKDIV + 1). EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 633: Phy Acknowledge Status Register (Alive)
The PHY indicates it does not have a link or fails to acknowledge the read transaction The PHY with the corresponding address has a link and the PHY acknowledges the read transaction. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 634: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)
An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 635: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)
An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 and the LINKINTENB bit in USERPHYSEL0 is set to 1. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 636: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)
No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 637: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)
The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed and the corresponding bit in USERINTMASKSET is set to 1. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 638: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)
MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 639: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)
MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 640: Mdio User Access Register 0 (Useraccess0)
0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 641: Mdio User Phy Select Register 0 (Userphysel0)
Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. Reserved Reserved PHYADRMON 0-1Fh PHY address whose link status is to be monitored. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 642: Mdio User Access Register 1 (Useraccess1)
0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 643: Mdio User Phy Select Register 1 (Userphysel1)
Reserved PHY address whose link status is to be monitored. PHYADRMON 0-1Fh PHY address whose link status is to be monitored. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 644: 17.3.3 Emac Module Registers
Receive Channel 6 Free Buffer Count Register Section 17.3.3.28 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 17.3.3.28 160h MACCONTROL MAC Control Register Section 17.3.3.29 EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 645 Section 17.3.3.49 670h RX4CP Receive Channel 4 Completion Pointer Register Section 17.3.3.49 674h RX5CP Receive Channel 5 Completion Pointer Register Section 17.3.3.49 SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 646 288h RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register Section 17.3.3.50.35 28Ch RXDMAOVERRUNS Receive DMA Overruns Register Section 17.3.3.50.36 EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 647: Transmit Revision Id Register (Txrevid)
Table 17-39. Transmit Control Register (TXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved TXEN Transmit enable Transmit is disabled. Transmit is enabled. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 648: Transmit Teardown Register (Txteardown)
Teardown transmit channel 2 Teardown transmit channel 3 Teardown transmit channel 4 Teardown transmit channel 5 Teardown transmit channel 6 Teardown transmit channel 7 EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 649: Receive Revision Id Register (Rxrevid)
Table 17-42. Receive Control Register (RXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved RXEN Receive enable Receive is disabled. Receive is enabled. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 650: Receive Teardown Register (Rxteardown)
Teardown receive channel 2 Teardown receive channel 3 Teardown receive channel 4 Teardown receive channel 5 Teardown receive channel 6 Teardown receive channel 7 EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 651: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)
TX2PEND TX2PEND raw interrupt read (before mask) TX1PEND TX1PEND raw interrupt read (before mask) TX0PEND TX0PEND raw interrupt read (before mask) SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 652: Transmit Interrupt Status (Masked) Register (Txintstatmasked)
TX4PEND masked interrupt read TX3PEND TX3PEND masked interrupt read TX2PEND TX2PEND masked interrupt read TX1PEND TX1PEND masked interrupt read TX0PEND TX0PEND masked interrupt read EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 653: Transmit Interrupt Mask Set Register (Txintmaskset)
Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 654: Transmit Interrupt Mask Clear Register (Txintmaskclear)
Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 655: Mac Input Vector Register (Macinvector)
Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. Bit 8 is RX0THRESHPEND. RXPEND 0-FFh Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 656: Mac End Of Interrupt Vector Register (Maceoivector)
Acknowledge C1MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Acknowledge C2RXTHRESH Interrupt Acknowledge C2RX Interrupt Acknowledge C2TX Interrupt Acknowledge C2MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Ch-1Fh Reserved EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 657: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)
RX2PEND RX2PEND raw interrupt read (before mask) RX1PEND RX1PEND raw interrupt read (before mask) RX0PEND RX0PEND raw interrupt read (before mask) SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 658: Receive Interrupt Status (Masked) Register (Rxintstatmasked)
RX4PEND masked interrupt read RX3PEND RX3PEND masked interrupt read RX2PEND RX2PEND masked interrupt read RX1PEND RX1PEND masked interrupt read RX0PEND RX0PEND masked interrupt read EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 659: Receive Interrupt Mask Set Register (Rxintmaskset)
Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. RX0MASK Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 660: Receive Interrupt Mask Clear Register (Rxintmaskclear)
Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. RX0MASK Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 661: Mac Interrupt Status (Unmasked) Register (Macintstatraw)
Value Description 31-2 Reserved Reserved HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read. STATPEND Statistics pending interrupt (STATPEND); masked interrupt read. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 662: Mac Interrupt Mask Set Register (Macintmaskset)
Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. STATMASK Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 663: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)
/ code errors and undersized are short frames without errors. Short frames are filtered. Short frames are transferred to memory. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 664 RXMULTCH bits. Multicast frames are filtered. Multicast frames are copied to the channel selected by RXMULTCH bits. Reserved Reserved EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 665 Select channel 5 to receive multicast frames Select channel 6 to receive multicast frames Select channel 7 to receive multicast frames SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 666: Receive Unicast Enable Set Register (Rxunicastset)
Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May be read. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 667: Receive Unicast Clear Register (Rxunicastclear)
RXCH0EN Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 668: Receive Maximum Length Register (Rxmaxlen)
15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 669: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)
Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 670: Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
The host must write this field with the number of buffers that have been freed due to host processing. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 671: Mac Control Register (Maccontrol)
The queue uses a fixed-priority (channel 7 highest priority) scheme to select the next channel for transmission. Reserved Reserved TXPACE Transmit pacing enable bit Transmit pacing is disabled. Transmit pacing is enabled. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 672 FULLDUPLEX bit. The loopback bit should be changed only when GMIIEN bit is deasserted. Loopback mode is disabled. Loopback mode is enabled. FULLDUPLEX Full duplex mode. Half-duplex mode is enabled. Full-duplex mode is enabled. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 673: Mac Status Register (Macstatus)
The host error occurred on transmit channel 5 The host error occurred on transmit channel 6 The host error occurred on transmit channel 7 SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 674 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive. Transmit flow control is active. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 675: Emulation Control Register (Emcontrol)
Two 64-byte packet cells required to be in the transmit FIFO. Three 64-byte packet cells required to be in the transmit FIFO. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 676: Mac Configuration Register (Macconfig)
If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred. A software reset has not occurred. A software reset has occurred. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 677: Mac Source Address Low Bytes Register (Macsrcaddrlo)
MAC source address bits 31-24 (byte 3) 15-8 MACSRCADDR4 0-FFh MAC source address bits 39-32 (byte 4) MACSRCADDR5 0-FFh MAC source address bits 47-40 (byte 5) SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 678: Mac Hash Address Register 1 (Machash1)
Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. If a hash table bit is set, then a group address that hashes to that bit index is accepted. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 679: Back Off Random Number Generator Test Register (Bofftest)
IPG time is not stretched to four times the normal value. Transmit pacing helps reduce capture effects, which improves overall network bandwidth. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 680: Receive Pause Timer Register (Rxpause)
The transmit pause timer is loaded by a received (incoming) pause frame, and then decremented at slot time intervals down to 0, at which time EMAC transmit frames are again enabled. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 681: Mac Address Low Bytes Register (Macaddrlo)
MATCHFILT is cleared to 0. 15-8 MACADDR0 0-FFh MAC address lower 8-0 bits (byte 0) MACADDR1 0-FFh MAC address bits 15-8 (byte 1) SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 682: Mac Address High Bytes Register (Macaddrhi)
16 bits of the address to the MACADDRLO register. Since all eight addresses share the upper 40 bits of the address, the MACADDRHI register only needs to be written the first time. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 683: Transmit Channel N Dma Head Descriptor Pointer Register (Txnhdp)
Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0 on reset. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 684: Transmit Channel N Completion Pointer Register (Txncp)
The EMAC uses the value written to determine if the interrupt should be deasserted. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 685: Statistics Register
Had no CRC error, alignment error, or code error Section 17.2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 686 Overruns have no effect on this statistic. CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 687 The address matching process decided that the frame should be discarded (filtered) because it did not match the unicast, broadcast, or multicast address, and it did not match due to promiscuous mode. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 688 Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Was any length • Had no late or excessive collisions, no carrier loss, and no underrun EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 689 When the EMAC is in half-duplex mode, flow control is active, and a frame reception begins. CRC errors have no effect on this statistic. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 690 The number of frames sent by the EMAC that experienced FIFO underrun. Late collisions, CRC errors, carrier loss, and underrun have no effect on this statistic. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 691 Was 128-bytes to 255-bytes long CRC errors, alignment/code errors, underruns, and overruns do not affect the recording of frames in this statistic. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 692 The objective of this statistic is to give a reasonable indication of Ethernet utilization. EMAC/MDIO Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 693 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. SPRUH91D – March 2013 – Revised September 2016 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 694: External Memory Interface A (Emifa)
EMIFA SDRAM is supported on your device..........................Topic Page ..................... 18.1 Introduction ..................... 18.2 Architecture ..................18.3 Example Configuration ......................18.4 Registers External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 695: 18.1 Introduction
The EMIFA SDRAM interface is not supported on all devices, see your device-specific data manual to see if the EMIFA SDRAM is supported on your device. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 696: 18.2.1 Clock Control
When interfacing to an asynchronous device, this pin provides a signal which is active-low during the strobe period of an asynchronous write access cycle. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 697: Emifa Pins Specific To Sdram
EMIFA asynchronous read/write control. This pin stays high during reads and stays low during writes (same duration as CS). SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 698: 18.2.4 Sdram Controller And Interface
EMA_A[12:11] EMA_A[10] EMA_A[9:0] Bank/X ACTV Bank READ Bank Column Column Bank Column Column Mode Mode Mode REFR SLFR External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 699: Timing Waveform Of Sdram Pre Command
16-bit interface, refer to Table 18-6 for list of commonly-supported SDRAM devices and the required connections for the address pins. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 700: Emifa To 2M × 16 × 4 Bank Sdram Interface
128M bits ×16 SDRAM A[11:0] EMIFA EMA_A[11:0] 256M bits SDRAM A[12:0] EMIFA EMA_A[12:0] 512M bits SDRAM A[12:0] EMIFA EMA_A[12:0] External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 701: Description Of The Sdram Configuration Register (Sdcr)
/ (Required SDRAM Refresh Rate) EMA_CLK More information about the operation of the SDRAM refresh controller can be found in Section 18.2.4.6. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 702: Description Of The Sdram Timing Register (Sdtimr)
(a) Issuing a PRE command with EMA_A[10] held high if any banks are open (b) Issuing an REF command External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 703: Sdram Load Mode Register Command
2. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device. The timing parameters should be taken from the SDRAM datasheet. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 704: Refresh Urgency Levels
Refresh Release urgency level is reached. At that point, the EMIFA can begin servicing any new read or write requests. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 705 EMA_CLK using the PLL Controller. If the frequency of EMA_CLK changes while the SDRAM is not in Self-Refresh Mode, Procedure B in Section 18.2.4.5 should be followed to reinitialize the device. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 706 If the PD bit is cleared while in the power-down state, the EMIFA will come out of the power-down state. The EMIFA: • Drives EMA_SDCKE high. • Enters its idle state. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 707: Timing Waveform For Basic Sdram Read Operation
NOP commands between various commands during an access. Refer to the register description of SDTIMR in Section 18.4.6 for more details on the various timing parameters. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 708: Timing Waveform For Basic Sdram Write Operation
NOP commands during various cycles of an access. Refer to the register description of SDTIMR in Section 18.4.6 for more details on the various timing parameters. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 709: Mapping From Logical Address To Emifa Pins For 16-Bit Sdram
NOTE: The upper bit of the Row Address is used only when addressing 256-Mbit and 512-Mbit SDRAM memories. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 710: 18.2.5 Asynchronous Controller And Interface
EMA_CS[n], n = 2, 3, 4, or 5. Figure 18-7. EMIFA Asynchronous Interface EMIFA EMA_CS[n] EMA_WE EMA_OE EMA_WAIT EMA_D[x:0] EMA_WE_DQM[x:0] EMA_A[x:0] EMA_BA[1:0] External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 711: Emifa To 8-Bit/16-Bit Memory Interface
EMIF to 16-bit memory interface Figure 18-9. Common Asynchronous Interface EMIFA 16−bit asynchronous device EMA_CS[n] EMA_WE EMA_WE_DQM[1:0] BE[1:0] EMA_D[15:0] DQ[15:0] SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 712: Description Of The Asynchronous M Configuration Register (Cencfg)
The EMA_WAIT pin is not available on all devices; therefore, this field is reserved on those devices. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 713: Description Of The Asynchronous Wait Cycle Configuration Register (Awcc)
NAND Flash Mode. The EMA_WAIT pin is not available on all devices; therefore, this register is reserved on those devices. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 714 EMIFA interrupts. Extended Wait Mode should not be used while in NAND Flash Mode. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 715: Description Of The Emifa Interrupt Mask Set Register (Intmskset)
If so, the EMIFA proceeds to the setup period of the operation. If it is no longer the highest priority task, the EMIFA terminates the operation. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 716: Timing Waveform Of An Asynchronous Read Cycle In Normal Mode
Figure 18-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enable EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 717: Asynchronous Write Operation In Normal Mode
If this is the case, the EMIFA instead enters directly into the turnaround period for the pending read or write operation. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 718: Timing Waveform Of An Asynchronous Write Cycle In Normal Mode
Figure 18-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enable EMA_A/EMA_BA Address Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 719: Asynchronous Read Operation In Select Strobe Mode
If this is the case, the EMIFA instead enters directly into the turnaround period for the pending read or write operation. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 720: Timing Waveform Of An Asynchronous Read Cycle In Select Strobe Mode
Figure 18-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enables EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 721: Asynchronous Write Operation In Select Strobe Mode
If this is the case, the EMIFA instead enters directly into the turn-around period for the pending read or write operation. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 722: Timing Waveform Of An Asynchronous Write Cycle In Select Strobe Mode
Figure 18-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enables EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 723: Description Of The Nand Flash Control Register (Nandfcr)
NOTE: The EMIFA will not control the NAND Flash device's write protect pin. The write protect pin must be controlled outside of the EMIFA. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 724: Emifa To Nand Flash Interface
See Section 18.2.5.6.8 for workaround. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 725 5) bit. Figure 18-15 shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 726: Ecc Value For 8-Bit Nand Flash
If bit errors fall into more than four bytes, the ECC engine will report that there are too many errors to correct. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 727 XORing the error word with the error value from the NAND Flash error value 1-2 registers (NANDERRVAL[2:1]). SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 728 R_SETUP and R_STROBE fields must be greater than 4 for the EMIFA to recognize the EMA_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in CEnCFG. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 729: 18.2.6 Data Bus Parking
Figure 18-16. EMIFA Reset Block Diagram EMIFA CHIP_RST Hard Reset Memory from PLL Controller Registers State MOD_G_RST EMIFA Machine SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 730: 18.2.8 Interrupt Support
See Section 18.4 for complete details on the register fields. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 731: 18.2.9 Edma Event Support
For details on EMIFA pin multiplexing, see your device-specific data manual. 18.2.11 Memory Map For information describing the device memory-map, see your device-specific data manual. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 732: 18.2.12 Priority And Arbitration
See Section 18.2.4.7 for details on the operation of the EMIFA when in the self-refresh state. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 733: 18.2.13 System Considerations
The system should be analyzed to make sure that this worst-case request delay is acceptable. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 734: 18.2.14 Power Management
EMA_SDCKE remains low until any request arrives. Refer to Section 18.2.4.8 for more details on placing EMIFA in power down mode. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 735: 18.2.15 Emulation Considerations
18.2.15 Emulation Considerations EMIFA memory controller will remain fully functional during emulation halts, to allow emulation access to external memory. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 736: 18.3 Example Configuration
Table 18-26. SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface Field Value Purpose 1 then 0 To place the EMIFA into the self refresh state External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 737: Example Configuration Interface
EMA_A[18:0] A[11:0] LDQM EMA_WE_DQM[0] UDQM EMA_WE_DQM[1] DQ[15:0] EMA_D[15:0] EMA_CS[3] EMA_OE TC5515100FT-12 EMA_WAIT A[0] A[19:1] DQ[15:0] RY/BY BYTE0 BYTE1 SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 738: Sdram Timing Register (Sdtimr)
Figure 18-19. SDRAM Timing Register (SDTIMR) 0 0110 T_RFC T_RP Rsvd T_RCD Rsvd T_WR 0100 0110 0000 T_RAS T_RC Rsvd T_RRD Reserved External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 739: Sdram Self Refresh Exit Timing Register (Sdsretr)
Figure 18-21. SDRAM Refresh Control Register (SDRCR) 0 0000 0000 0000 Reserved Reserved 0 0110 0001 1010 (61Ah) Reserved SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 740: Sdram Configuration Register (Sdcr)
0 0000 Reserved Reserved Reserved 00 0000 Reserved Reserved Reserved Reserved Reserved Reserved BIT11_9LOCK Reserved IBANK Reserved PAGESIZE External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 741: Emifa Input Timing Requirements
R_SETUP width in EMIFA clock cycles minus 1 cycle. R_SETUP + R_STROBE ≥ R_SETUP ) R_STROBE ) R_HOLD w R_HOLD w SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 742: Timing Waveform Of An Asram Read
Address valid to end of Write Data Setup time Write Recovery time Data Hold time Write Cycle time External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 743: Timing Waveform Of An Asram Write
W_SETUP ) W_STROBE ) W_HOLD w Figure 18-24. Timing Waveform of an ASRAM Write Setup Hold Strobe EMA_CS[n] EMA_A[x:0] EMA_BA[1:0] EMA_WE EMA_D[x:0] SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 744: Asram Timing Requirements With Pcb Delays
R_SETUP ) R_STROBE ) R_HOLD w (m) * t EM_D EM_A R_HOLD w (m) ) t EM_CS EM_D TA w External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 745: Timing Waveform Of An Asram Read With Pcb Delays
CEnCFG is programmed in terms of EMIFA clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIFA clock cycles minus 1 cycle. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 746: Timing Waveform Of An Asram Write With Pcb Delays
EMA_CS[n] (ASRAM) EMA_A[x:0]/ EMA_BA[1:0] EMA_A EMA_A EMA_A[x:0]/ EMA_BA[1:0] (ASRAM) EMA_WE EMA_WE EMA_WE EMA_WE (ASRAM) EMA_D[x:0] EMA_D EMA_D EMA_D[x:0] (ASRAM) External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 747: Emifa Timing Requirements For Tc5516100Ft-12 Example
Delay on EMA_WE from EMIFA to ASRAM. EMA_WE is driven by EMIF. 0.36 EM_WE Delay on EMA_D from EMIFA to ASRAM. EMA_D is driven by EMIF. 0.45 EM_D SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 748 * 3 w * 3 w * 1.8 Therefore, W_SETUP = 0, W_STROBE = 0, and W_HOLD = 0. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 749: Configuring Ce3Cfg For Tc5516100Ft-12 Example
Recommended Margin Output Setup 10 nS Output Hold 10 nS Input Setup 10 nS Input Hold 10 nS SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 750: Emifa Read Timing Requirements
EMIFA and NAND Flash AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 751: Timing Waveform Of A Nand Flash Read
TA w max Figure 18-27. Timing Waveform of a NAND Flash Read Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_OE EMA_D[7:0] SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 752: Nand Flash Write Timing Requirements
W_SETUP w max W_STROBE w W_SETUP + W_STROBE ≥ W_HOLD w max W_SETUP ) W_STROBE ) W_HOLD w External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 753: Timing Waveform Of A Nand Flash Command Write
Figure 18-29. Timing Waveform of a NAND Flash Address Write Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 754: Timing Waveform Of A Nand Flash Data Write
Figure 18-30. Timing Waveform of a NAND Flash Data Write Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 755: Emifa Timing Requirements For Hy27Ua081G1M Example
Data Setup time CLE Hold time ALE Hold time CS Hold time Data Hold time Write Cycle time SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 756 Therefore with a 10 nS margin added in, W_SETUP ≥ 0, W_STROBE ≥ 6, and W_HOLD ≥ 1. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 757: Configuring Ce2Cfg For Hy27Ua081G1M Example
• CS3NAND = 0. NAND Flash mode is disabled. CS2NAND NAND Flash mode for chip select 2. • CS5NAND = 1. NAND Flash mode is enabled. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 758: External Memory Interface (Emifa) Registers
NAND Flash 4-Bit ECC Error Value Register 1 Section 18.4.22 NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 Section 18.4.23 External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 759: Module Id Register (Midr)
R/W-0 R/W-0 Reserved MAX_EXT_WAIT R/W-80h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 760: Asynchronous Wait Cycle Configuration Register (Awccr) Field Descriptions
× 16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 761: Sdram Configuration Register (Sdcr)
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 762 10 column address bits (1024 elements per row) 11 column address bits (2048 elements per row) 4h-7h Reserved External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 763: Sdram Refresh Control Register (Sdrcr)
Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the SDRAM timing register (SDTIMR). SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 764: Asynchronous N Configuration Register (Cencfg)
Read setup width in the format n - 1, where n = number of EMA_CLK cycles. See Section 18.2.5.3 details. 0h = Divide-by-1 1h = Divide-by-2 … 2h – 1Fh = Divide-by-3 to Divide-by-16 External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 765 Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. 8-bit data bus 16-bit data bus 2h-3h Reserved SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 766: Sdram Timing Register (Sdtimr)
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 767: Sdram Self Refresh Exit Timing Register (Sdsretr)
This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, minus one. T_XS = Txsr / t EMA_CLK SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 768: Emifa Interrupt Raw Register (Intraw)
Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the AT_MASKED bit in the EMIFA interrupt masked register (INTMSK). External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 769: Emifa Interrupt Mask Register (Intmsk)
Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit as well as the AT bit in the EMIFA interrupt raw register (INTRAW). SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 770: Emifa Interrupt Mask Set Register (Intmskset)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 sets this bit and the AT_MASK_CLR bit in the EMIFA interrupt mask clear register (INTMSKCLR). External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 771: Emifa Interrupt Mask Clear Register (Intmskclr)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 clears this bit and the AT_MASK_SET bit in the EMIFA interrupt mask set register (INTMSKSET). SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 772: Nand Flash Control Register (Nandfcr)
Do not start ECC calculation. Start ECC calculation on data for NAND Flash on EMA_CS2. Reserved Reserved External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 773 Using NAND Flash on EMA_CS3. CS2NAND NAND Flash mode for chip select 2. Not using NAND Flash. Using NAND Flash on EMA_CS2. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 774: Nand Flash Status Register (Nandfsr)
(AWCC) has no effect on WAITST. EMA_WAIT[n] pin is low. EMA_WAIT[n] pin is high. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 775: Nand Flash N Ecc Register (Nandfnecc)
ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 776: Nand Flash 4-Bit Ecc Load Register (Nand4Biteccload)
0-3FFh 4-bit ECC load. This value is used to load the ECC values when performing the Syndrome calculation during reads. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 777: Nand Flash 4-Bit Ecc Register 1 (Nand4Bitecc1)
0-3FFh Calculated 4-bit ECC or Syndrom Value4. 15-10 Reserved Reserved 4BITECCVAL3 0-3FFh Calculated 4-bit ECC or Syndrom Value3. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 778: Nand Flash 4-Bit Ecc Register 3 (Nand4Bitecc3)
0-3FFh Calculated 4-bit ECC or Syndrom Value8. 15-10 Reserved Reserved 4BITECCVAL7 0-3FFh Calculated 4-bit ECC or Syndrom Value7. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 779: Nand Flash 4-Bit Ecc Error Address Register 1 (Nanderradd1)
0-3FFh Calculated 4-bit ECC Error Address 4. 15-10 Reserved Reserved 4BITECCERRADD3 0-3FFh Calculated 4-bit ECC Error Address 3. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 780: Nand Flash 4-Bit Ecc Error Value Register 1 (Nanderrval1)
0-3FFh Calculated 4-bit ECC Error Value 4. 15-10 Reserved Reserved 4BITECCERRVAL3 0-3FFh Calculated 4-bit ECC Error Value 3. External Memory Interface A (EMIFA) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 781: External Memory Interface B (Emifb)
This chapter describes the external memory interface B (EMIFB)..........................Topic Page ..................... 19.1 Introduction ..................... 19.2 Architecture ..................19.3 Example Configuration ......................19.4 Registers SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 782: Emifb Functional Block Diagram
EMB_RAS Crossbar FIFO EMB_WE Master EMB_CLK SDRAM Peripherals Interface EMB_SDCKE Read (USB, UHPI...) EMB_BA[1:0] FIFO EMB_A[x:0] EMB_D[x:0] EMB_WE_DQM[x:0] External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 783: Emif Pins Used To Access Sdram
This pin is connected to the RAS pin of the attached SDRAM device and is used for sending commands to the device. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 784: Emif Sdram Commands
No operation. The NOP command is issued during all cycles in which one of the above commands is not issued. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 785: Timing Waveform Of Sdram Pre Command
Figure 19-2. Timing Waveform of SDRAM PRE Command EMB_CLK EMB_CS EMB_WE_DQM EMB_BA Bank EMB_A[10] = 0 EMB_A EMB_RAS EMB_CAS EMB_WE SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 786: Emifb To 2M × 16 × 4 Bank Sdram Interface
2M x 32 x 4 Bank EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] BA[1:0] EMB_A[11:0] A[11:0] EMB_WE_DQM[3:0] DQM[3:0] EMB_D[31:0] DQ[31:0] External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 787: Emifb To Dual 4M × 16 × 4 Bank Sdram Interface
EMB_A[12:0] ×32 SDRAM A[11:0] EMIFB EMB_A[11:0] 512M bits ×16 SDRAM A[12:0] EMIFB EMB_A[12:0] ×32 SDRAM A[12:0] EMIFB EMB_A[12:0] SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 788: Example Of 16-Bit Emifb Address Pin Connections
This field value affects the mapping of logical addresses to SDRAM row, column, and bank addresses. See Section 19.2.6.10 for details. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 789: Description Of The Sdram Refresh Control Register (Sdrfc)
The T_CKE field fixes the minimum time between CKE transitions. This parameter is set to satisfy the value for the attached SDRAM device. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 790: Description Of The Sdram Configuration 2 Register (Sdcfg2)
These bits are set according to the PASR field in the drive strength) Compensated Self Refresh) SDRAM configuration 2 register (SDCFG2). External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 791: Sdram/Mobile Sdram Load Mode Register Command
SDRAM. The remainder of this section details the EMIFB's refresh scheme and provides an example for determining the appropriate value to place in the REFRESH_RATE field of SDRFC. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 792: Refresh Urgency Levels
REFRESH_RATE can be calculated as: REFRESH_RATE = 133 MHz × 64 ms/8192 REFRESH_RATE = 1039.06 REFRESH_RATE = 1039 cycles = 40Fh cycles External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 793 (driving EMB_SDCKE high) and executes the requests; after which it again goes back to the power- down state (driving EMB_SDCKE low). SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 794 Refresh banks 0 and 1 Refresh bank 0 Reserved Reserved Refresh 1/2 of bank 0 Refresh 1/4 of bank 0 Reserved External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 795: Timing Waveform For Basic Sdram Read Operation
NOP commands between various commands during an access. Refer to the register description of SDTIM1 and SDTIM2 for more details on the various timing parameters. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 796: Timing Waveform For Basic Sdram Write Operation
NOP commands during various cycles of an access. Refer to the register description of SDTIM1 and SDTIM2 for more details on the various timing parameters. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 797: Example Mapping From Logical Address To Emifb Pins For 32-Bit Sdram
WE_DQM[3:0] Row Address Column Address WE_DQM[3:0] Row Address BA[0] Column Address WE_DQM[3:0] Row Address BA[1:0] Column Address WE_DQM[3:0] SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 798: Example Mapping From Logical Address To Emifb Pins For 16-Bit Sdram
ROWSIZE = 3 => 12 bits PAGESIZE = 3 => 11 bits ROWSIZE = 4 => 13 bits External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 799: Emifb Memory Controller Fifo Block Diagram
Write FIFO Write Data to memory Read FIFO Read data from memory Registers Command Data SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 800 From the same master, any read to the same location (or within 2048 bytes) as a previous write will complete in order External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 801 The EDMA peripheral does not need to implement the above workaround. If a peripheral is not listed here, then the above workaround is required. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 802: Emifb Memory Controller Reset Block Diagram
EMIFB memory controller is a DMA slave peripheral and therefore does not generate DMA events. Data read and write requests may be made directly, by masters and the DMA. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 803: Emifb Memory Controller Power And Sleep Controller Diagram
EMB_SDCKE remains low until any request arrives. Refer to Power-Down Mode for more details on placing EMIFB in power-down mode. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 804 Section 19.2.6.7 for details on self-refresh mode. After auto wake, EMIFB is in enable state and clocks run continuously. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 805: Emulation Considerations
SYSCLK domain of the PLL Controller. Once the PLL has been reprogrammed, remove the SDRAM from Self-Refresh by clearing the LP_MODE bit in SDRFC. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 806: Connecting Emifb Memory Controller For 32-Bit Connection
4M x 16 x 4 Bank EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] BA[1:0] EMB_A[12:0] A[12:0] EMB_WE_DQM[0] LDQM EMB_WE_DQM[1] UDQM EMB_D[15:0] DQ[15:0] External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 807: Sdcfg Configuration
This bit is ignored when LP_MODE=0. REFRESH_RATE 40Eh Set to 40Eh SDRAM clock cycles to meet the SDRAM memory refresh rate requirement. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 808: Sdtim1 Configuration
Register field value must be ≤ the calculated value Register field value must be ≥ the calculated value External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 809: Revision Id Register (Revid)
Table 19-24. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4033 131Fh Revision ID value of EMIFB. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 810: Sdram Configuration Register (Sdcfg)
When this bit is 1 and SDREN = 1, then mSDR is enabled. Reserved All writes to these bit(s) must always have a value of 0. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 811 512-word pages requiring 9 column address bits. 1024-word pages requiring 10 column address bits. 2048-word pages requiring 11 column address bits. 4h-7h Reserved SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 812: Sdram Refresh Control Register (Sdrfc)
Writing a value < 0100h to this field causes it to be loaded with 2 × T_RFC value from SDRAM timing 1 register (SDTIM1). The required refresh rate is derived from the SDRAM device data sheet. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 813: Sdram Timing 1 Register (Sdtim1)
)) / (4 × t ) - 1. Reserved All writes to these bit(s) must always have a value of 0. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 814: Sdram Timing 2 Register (Sdtim2)
Minimum number of EMB_CLK cycles between EMB_SDCKE changes, minus one. This field must satisfy t for the SDRAM device. T_CKE = (t /EMIF_CLK) - 1 External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 815: Sdram Configuration 2 Register (Sdcfg2)
11 row address bits used. 12 row address bits used. 13 row address bits used. 14 row address bits used. 6h-7h Reserved SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 816: Peripheral Bus Burst Priority Register (Bprio)
Recommended setting for typical system operation is between 10h and 20h. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 817: Performance Counter 1 Register (Pc1)
32-bit counter that can be configured as specified in the performance counter configuration register (PCC) and the performance counter master region select register. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 818: Performance Counter Configuration Register (Pcc)
Any writes to these bit(s) must always have a value of 0. CNTR1_CFG 0-Fh Filter configuration for performance counter 1 register (PC1). Refer to Table 19-34 details. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 819: Performance Counter Filter Configuration
As the value of this counter approaches 100%, the number of cycles the EMIFB has a command in the command FIFO to service approaches 100%. Ah-Fh Reserved SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 820: Performance Counter Master Region Select Register (Pcmrs)
Region select for performance counter 1 register (PC1). PC1 counts total SDRAM accesses. 1h-6h Reserved PC1 counts total EMIFB memory-mapped register accesses. 8h-Fh Reserved External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 821: Performance Counter Time Register (Pct)
Reserved All writes to these bit(s) must always have a value of 0. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 822: Interrupt Mask Register (Imr)
Line trap occurred due to use of unsupported addressing mode (only set if the LTMSET bit in IMSR is set). Reserved All writes to these bit(s) must always have a value of 0. External Memory Interface B (EMIFB) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 823: Interrupt Mask Set Register (Imsr)
Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred. Reserved All writes to these bit(s) must always have a value of 0. SPRUH91D – March 2013 – Revised September 2016 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 824: General-Purpose Input/Output (Gpio)
This chapter describes the GPIO..........................Topic Page ..................... 20.1 Introduction ..................... 20.2 Architecture ......................20.3 Registers General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 825: Introduction
The GPIO peripheral connects to external devices. While it is possible that the software implements some standard connectivity protocol over GPIO, the GPIO peripheral itself is not compliant with any such standards. SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 826: Gpio Block Diagram
20.2.4 Endianness Considerations The GPIO operation is independent of endianness; therefore, there are no endianness considerations for the GPIO module. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 827: Gpio Register Bits And Banks Associated With Gpio Signals
GP1[10] register_name01 Bit 26 GP1P10 GP1[11] register_name01 Bit 27 GP1P11 GP1[12] register_name01 Bit 28 GP1P12 GP1[13] register_name01 Bit 29 GP1P13 SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 828 GP4[9] register_name45 Bit 9 GP4P9 GP4[10] register_name45 Bit 10 GP4P10 GP4[11] register_name45 Bit 11 GP4P11 GP4[12] register_name45 Bit 12 GP4P12 General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 829 GP7[8] register_name67 Bit 24 GP7P8 GP7[9] register_name67 Bit 25 GP7P9 GP7[10] register_name67 Bit 26 GP7P10 GP7[11] register_name67 Bit 27 GP7P11 SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 830: Using A Gpio Signal As An Output
GPIO input data register (IN_DATA) associated with the desired GPIO signal. IN_DATA contains the actual logic state on the external signal. For detailed information on these registers, see Section 20.3. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 831: Using A Gpio Signal As An Input
PSC reset, followed by GPIO clock enable) will result in the default configuration register settings. For details on the PSC, see the Power and Sleep Controller (PSC) chapter. SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 832: Initialization
Write a logic 1 to the associated bit in SET_FAL_TRIG. • Write a logic 1 to the associated bit in CLR_RIS_TRIG. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 833: Edma Event Support
20.2.13 Emulation Considerations The GPIO peripheral is not affected by emulation suspend events (such as halts and breakpoints). SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 834: Gpio Registers
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register Section 20.3.11 INTSTAT45 GPIO Banks 4 and 5 Interrupt Status Register Section 20.3.12 General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 835: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 20-3. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4483 0105h Peripheral Revision SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 836: Gpio Interrupt Per-Bank Enable Register (Binten)
Bank 0 interrupt enable is used to disable or enable the bank 0 interrupts (events from GP0[15-0]). Bank 0 interrupts are disabled. Bank 0 interrupts are enabled. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 837: Gpio Banks 0 And 1 Direction Register (Dir01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-1 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 838: Gpio Bank 8 Direction Register (Dir8)
Direction of pin GPk[j]. The GPkPj bit is used to control the direction (output = 0, input = 1) of pin j in GPIO bankk. GPk[j] is an output. GPk[j] is an input. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 839: Gpio Banks 0 And 1 Output Data Register (Out_Data01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 840: Gpio Bank 8 Output Data Register (Out_Data8)
The GPkPj bit is ignored when GPk[j] is configured as an input. GPk[j] is driven low. GPk[j] is driven high. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 841: Gpio Banks 0 And 1 Set Data Register (Set_Data01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 842: Gpio Bank 8 Set Data Register (Set_Data8)
GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. Reading the GPkPj bit returns the output drive state of GPk[j]. No effect. GPk[j] is set to output logic high. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 843: Gpio Banks 0 And 1 Clear Data Register (Clr_Data01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 844: Gpio Bank 8 Clear Data Register (Clr_Data8)
GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. Reading the GPkPj bit returns the output drive state of GPk[j]. No effect. GPk[j] is set to output logic low. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 845: Gpio Banks 0 And 1 Input Data Register (In_Data01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 LEGEND: R = Read only; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 846: Gpio Bank 8 Input Data Register (In_Data8)
Status of pin GPk[j]. Reading the GPkPj bit returns the state of pin j in GPIO bank k. GPk[j] is logic low. GPk[j] is logic high. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 847: Gpio Banks 0 And 1 Set Rise Trigger Register (Set_Ris_Trig01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 848: Gpio Bank 8 Set Rise Trigger Register (Set_Ris_Trig8)
No effect. Interrupt is caused by a low-to-high transition on GPk[j]. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 849: Gpio Banks 0 And 1 Clear Rise Trigger Register (Clr_Ris_Trig01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 850: Gpio Bank 8 Clear Rise Trigger Register (Clr_Ris_Trig8)
GPk[j]. Therefore, this bit will be one in both registers if the function is enabled, and zero in both registers if the function is disabled. No effect. No interrupt is caused by a low-to-high transition on GPk[j]. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 851: Gpio Banks 0 And 1 Set Rise Trigger Register (Set_Fal_Trig01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 852: Gpio Bank 8 Set Rise Trigger Register (Set_Fal_Trig8)
No effect. Interrupt is caused by a high-to-low transition on GPk[j]. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 853: Gpio Banks 0 And 1 Clear Rise Trigger Register (Clr_Fal_Trig01)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 854: Gpio Bank 8 Clear Rise Trigger Register (Clr_Fal_Trig8)
No effect. No interrupt is caused by a high-to-low transition on GPk[j]. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 855: Gpio Banks 0 And 1 Interrupt Status Register (Intstat01)
LEGEND: R/W = Read/Write; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset SPRUH91D – March 2013 – Revised September 2016 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 856: Gpio Bank 8 Interrupt Status Register (Intstat8)
Write a 1 to the GPkPj bit to clear the status bit; a write of 0 has no effect. No pending interrupt on GPk[j]. Pending interrupt on GPk[j]. General-Purpose Input/Output (GPIO) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 857: Host Port Interface (Hpi)
This chapter describes the host port interface (HPI)..........................Topic Page ..................... 21.1 Introduction ..................... 21.2 Architecture ......................21.3 Registers SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 858: Introduction
Memory-mapped peripheral identification register (PID) • Bus holders on host data and address buses (these are actually external to HPI module) Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 859: Hpi Block Diagram
HPIA type HCNTL1 Logic Increment high UHPI_HAS HPIC UHPI_HR/W Chip select UHPI_HCS Data UHPI_HDS1, UHPI_HDS2 strobes UHPI_HINT Ready UHPI_HRDY SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 860: Industry Standard(S) Compliance Statement
Logic used to communicate between the HPI and the DMA system that moves data to and from memory. This is independent of the EDMA system on the processor processor Entire system-on-chip Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 861: Hpi Pins
When the HPI drives UHPI_HRDY high, the HPI is not ready for the current host cycle to complete. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 862: Value On Optional Pins When Configured As General-Purpose I/O
When the GPIO_DIR2.HASZ bit is cleared to 0, configuring the UHPI_HAS pin as an input, writing to the GPIO_DAT2.HASZ bit has no effect. Reading from this bit will return the value on the UHPI_HAS pin. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 863: Protocol Description
HPID read cycle to an HPID write cycle, or conversely). Otherwise, the memory location accessed by the HPI DMA logic might not be the location intended by the host. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 864: Example Of Host-Processor Signal Connections
Data strobe1 UHPI_HDS1 Data strobe UHPI_HDS2 Data UHPI_HD[15:0] Ready UHPI_HRDY UHPI_HINT Interrupt Data strobing options are given in Section 21.2.6.4 Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 865 HPID, the HPI DMA logic reads the memory address from HPIAW and transfers the data from HPID to the addressed memory location. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 866: Hpi Strobe And Select Logic
Connect the strobe pin to UHPI_HDS1 or UHPI_HDS2, and connect the other strobe pin to logic-level 0. The UHPI_HR/W signal could be driven by a host address line in this case. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 867: Access Types Selectable With The Uhpi_Hcntl Signals
HPIC. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 868: Multiplexed-Mode Host Read Cycle
FIFO, transitions on UHPI_HRDY may or may not occur. For more information, Section 21.2.6.9. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 869: Multiplexed-Mode Host Write Cycle
FIFO, transitions on UHPI_HRDY may or may not occur. For more information, Section 21.2.6.9. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 870: Multiplexed-Mode Single-Halfword Hpic Cycle (Read Or Write)
The following sections describe the behavior of UHPI_HRDY during HPI register accesses. In all cases, the chip select signal, UHPI_HCS, must be asserted for UHPI_HRDY to go low. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 871: Uhpi_Hrdy Behavior During An Hpic Or Hpia Read Cycle In The Multiplexed Mode
UHPI_HCS UHP_HAS UHPI_HCNTL[1:0] UHPI_HR/W HHWIL Internal UHPI_HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword UHPI_HD[15:0 UHPI_HRDY SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 872: Uhpi_Hrdy Behavior During An Hpic Write Cycle In The Multiplexed Mode
UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL Interna HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword UHPI_HD[15:0] UHPI_HRDY Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 873: Autoincrementing Selected, Fifo Not Empty Before Write)
UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL Internal HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword UHPI_HD[15:0] UHPI_HRDY SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 874: Fifos In The Hpi
Read FIFO Burst reads Host reads Host read HPI DMA pointer write pointer Read FIFO control logic Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 875 As soon as the host activates a read cycle without autoincrementing, prefetching activity ceases until the occurrence of a FETCH command or an autoincrement read cycle. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 876 A nonautoincrement write cycle always should be preceded by the initialization of HPIAW or by another nonautoincrement access, so that the write FIFO is flushed beforehand. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 877 (internal HSTRB is held high), the FIFOs are held in reset, and host transactions are held off with an inactive UHPI_HRDY signal. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 878: Reset Considerations
7. Release the HPI logic from reset by clearing the HPIRST bit in HPIC. The HPI is now ready to perform data transactions. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 879: Host-To-Cpu Interrupt State Diagram
Writes of 0 have no effect. A hardware reset immediately clears DSPINT and thus clears an active host-to- CPU interrupt. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 880: Cpu-To-Host Interrupt State Diagram
For detailed information on power management procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 881: Hpi Registers
Section 21.3.8 HPIAW Host Port Interface Write Address Register Section 21.3.9 HPIAR Host Port Interface Read Address Register Section 21.3.10 SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 882: Revision Identification Register (Revid)
0, the SOFT bit selects the HPI mode. The SOFT bit selects the HPI mode. The HPI runs free regardless of the SOFT bit. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 883: Gpio Enable Register (Gpio_En)
Enable as GPIO for UHPI_HCS, UHPI_HDS1, UHPI_HDS2, UHPI_HR/W pins. Disable pins for GPIO. Pins functions as HPI signal. Enable pins for GPIO. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 884: Gpio Direction 1 Register (Gpio_Dir1)
Table 21-11. GPIO Data 1 Register (GPIO_DAT1) Field Descriptions Field Value Description 31-16 Reserved Reserved 15-0 Data read from/written to UHPI_HDn pin. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 885: Gpio Direction 2 Register (Gpio_Dir2)
UHPI_HCS pin is an output. HASZ Direction control for UHPI_HAS pin. UHPI_HAS pin is an input. UHPI_HAS pin is an output. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 886: Gpio Data 2 Register (Gpio_Dat2)
Data read from/written to UHPI_HDS1 pin. HCSZ Data read from/written to UHPI_HCS pin. HASZ Data read from/written to UHPI_HAS pin. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 887: Host Port Interface Control Register (Hpic)-Host Access Permissions
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 888: Host Port Interface Control Register (Hpic) Field Descriptions
Halfword ordering bit. HWOB affects both data and address transfers. HWOB must be initialized before the first data or address register access. First halfword is most significant. First halfword is least significant. Host Port Interface (HPI) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 889: Host Port Interface Write Address Register (Hpiaw)
Table 21-16. Host Port Interface Read Address Register (HPIAR) Field Descriptions Field Value Description 31-0 HPIAR 0-FFFF FFFFh Host port interface read address. SPRUH91D – March 2013 – Revised September 2016 Host Port Interface (HPI) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 890: Inter-Integrated Circuit (I2C) Module
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1..........................Topic Page ..................... 22.1 Introduction ..................... 22.2 Architecture ......................22.3 Registers Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 891: Introduction
The combined format in 10-bit addressing mode (the I2C sends the slave address the second byte every time it sends the slave address the first byte). SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 892: I2C Peripheral Block Diagram
22.1.4 Industry Standard(s) Compliance Statement The I2C peripheral is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 893: Multiple I2C Modules Connected
Figure 22-2. Multiple I2C Modules Connected TI device Pull-up resistors controller Serial data (I2Cx_SDA) Serial clock (I2Cx_SCL) TI device EPROM SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 894: Clocking Diagram For The I2C Peripheral
The I2C module must be operated with a prescaled module clock frequency of 6.7 to 13.3 MHz. The I2C prescaler register (ICPSC) must be configured to this frequency range. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 895: Synchronization Of Two I2C Clock Generators During Arbitration
(high) are not fixed and depend on the associated power supply level. See your device-specific data manual for more information. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 896: Bit Transfer On The I2C-Bus
(including the MST, STT, and STP bits). Figure 22-6. I2C Peripheral START and STOP Conditions I2Cx_SDA I2Cx_SCL START STOP condition (S) condition (P) Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 897: I2C Peripheral Data Transfer
= The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICM DR. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 898: I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing To Slave-Receiver (Fdf = 0, Xa = 1 In Icmdr)
= The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 899: Operating Modes Of The I2C Peripheral
(XSMT = 0 in ICSTR) after data has been transmitted. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 900: Ways To Generate A Nack Bit
• If STP = 0, make STP = 1 to generate a STOP condition. • Reset the peripheral (IRS = 0 in ICMDR). Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 901: Arbitration Procedure Between Two Master-Transmitters
I2Cx_SCL Device #1 lost arbitration and switches off Data from device #1 Data from device #2 Bus line I2Cx_SDA SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 902: Reset Considerations
Once the bus is determined to be available (the bus is not busy), the I2C is ready to proceed with the desired communication. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 903: Interrupt Support
If there is more than one pending interrupt flag, reading ICIVR clears the highest-priority interrupt flag. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 904: Descriptions Of The I2C Interrupt Events
I2C peripheral is acting as a master or a slave. For more information, see the description of the FREE bit in ICMDR (see Section 22.3.9). Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 905: Inter-Integrated Circuit (I2C) Registers
I2C Pin Data Out Register Section 22.3.19 ICPDSET I2C Pin Data Set Register Section 22.3.20 ICPDCLR I2C Pin Data Clear Register Section 22.3.21 SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 906: I2C Own Address Register (Icoar)
In 10-bit addressing mode (XA = 1 in ICMDR): bits 9-0 provide the 10-bit slave address of the I2C. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 907: I2C Interrupt Mask Register (Icimr)
Interrupt request is disabled. Interrupt request is enabled. Arbitration-lost interrupt enable bit Interrupt request is disabled. Interrupt request is enabled. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 908: I2C Interrupt Status Register (Icstr)
• The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset). Overrun is detected. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 909 • In the repeat mode (RM = 1): ARDY is set at the end of each data word transmitted from ICDXR. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 910 When AL is set to 1, the MST and STP bits of ICMDR are cleared, and the I2C becomes a slave- receiver. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 911: I2C Clock Low-Time Divider Register (Icclkl)
Clock high-time divide-down value of 1-65536. The period of the module clock is multiplied by (ICCH + d) to produce the high-time duration of the I2C serial on the I2Cx_SCL pin. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 912: I2C Data Count Register (Iccnt)
The start value loaded to the internal data counter is 65536. 1h-FFFFh The start value loaded to internal data counter is 1-65535. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 913: I2C Data Receive Register (Icdrr)
These reserved bit locations are always read as zeros. A value written to this field has no effect. 0-FFh Receive data. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 914: I2C Slave Address Register (Icsar)
In 10-bit addressing mode (XA = 1 in ICMDR): Bits 9-0 provide the 10-bit slave address that the I2C transmits when it is in the master-transmitter mode. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 915: I2C Data Transmit Register (Icdxr)
These reserved bit locations are always read as zeros. A value written to this field has no effect. 0-FFh Transmit data. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 916: I2C Mode Register (Icmdr)
STP has been set to generate a STOP condition when the internal data counter of the I2C counts down to 0. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 917 Free data format mode is disabled. Transfers use the 7-/10-bit addressing format selected by the XA bit. Free data format mode is enabled. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 918: Master-Transmitter/Receiver Bus Activity Defined By Rm, Stt, And Stp Bits
TRX identifies the role of the I2C: TRX = 0: The I2C is a receiver. TRX = 1: The I2C is a transmitter. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 919: Block Diagram Showing The Effects Of The Digital Loopback Mode (Dlb) Bit
ICDRR ICRSR From CPU or EDMA ICSAR From CPU or EDMA ICOAR ICXSR From CPU or EDMA ICDXR Address/data SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 920: I2C Interrupt Vector Register (Icivr)
Transmit-data-ready interrupt (ICXRDY) Stop condition detected interrupt (SCD) Address-as-slave interrupt (AAS). Lowest priority if multiple I2C interrupts are pending. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 921: I2C Extended Mode Register (Icemdr)
The transmit data ready interrupt is generated when the data in ICDXR is copied to ICXSR. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 922: I2C Prescaler Register (Icpsc)
I2C clock frequency = I2C input clock frequency/(IPSC + 1) Note: IPSC must be initialized while the I2C is in reset (IRS = 0 in ICMDR). Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 923: I2C Revision Identification Register 1 (Revid1)
LEGEND: R = Read only; -n = value after reset Table 22-21. I2C Revision Identification Register 2 (REVID2) Field Descriptions Field Value Description 31-0 REVID2 Peripheral Identification Number SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 924: I2C Dma Control Register (Icdmac)
Receive DMA enable . This bit controls the receive DMA event pin to the system. Always set this bit to DMA receive event is disabled. DMA receive event is enabled. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 925: I2C Pin Function Register (Icpfunc)
I2C in reset via the IRS bit when changing to/from GPIO mode via the PFUNC0 bit. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 926: I2C Pin Direction Register (Icpdir)
Controls the direction of the I2Cx_SCL pin when configured as GPIO. I2Cx_SCL pin functions as input. I2Cx_SCL pin functions as output. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 927: I2C Pin Data In Register (Icpdin)
Logic-low present at I2Cx_SCL pin, regardless of PFUNC bit setting. Logic-high present at I2Cx_SCL pin, regardless of PFUNC bit setting. During writes: Writes have no effect. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 928: I2C Pin Data Out Register (Icpdout)
During reads: Reads return register values, not GPIO pin levels. During writes: I2Cx_SCL pin is driven low. I2Cx_SCL pin is driven high. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 929: I2C Pin Data Set Register (Icpdset)
I2Cx_SCL GPIO pin. During reads: Reads return indeterminate values. During writes: No effect PDOUT0 bit is set to logic high. SPRUH91D – March 2013 – Revised September 2016 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 930: I2C Pin Data Clear Register (Icpdclr)
I2Cx_SCL GPIO pin. During reads: Reads return indeterminate values. During writes: No effect PDOUT0 bit is cleared to logic low. Inter-Integrated Circuit (I2C) Module SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 931: Liquid Crystal Display Controller (Lcdc)
LCD interface and a synchronous (raster-type) LCD interface. This chapter describes the LCDC..........................Topic Page ..................... 23.1 Introduction ..................... 23.2 Architecture ......................23.3 Registers SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 932: Lcd Controller
Output LCD_D[15:0] serializer FIFO Raster controller Registers LCD_VSYNC LCD_HSYNC LCD_PCLK control LIDD LCD_AC_ENB_CS registers controller LCD_MCLK read/ write Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 933: Input And Output Clocks
• Active (TFT) mode. LCD_PCLK continuously toggles as long as the Raster Controller is enabled. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 934 Active (TFT) mode. This signal acts as an output enable (OE) signal. It is used to signal the external LCD that the data is valid on the data bus (LCD_D[15:0]). Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 935: Lcd External I/O Signals
LIDD character: Read and write the command and data registers. LIDD graphics: Read and write the command and data registers. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 936: Register Configuration For Dma Engine Programming
The EOF1, EOF0, and DONE bits in the LCD_STAT register reflect the interrupt signal, regardless of being delivered to the system interrupt controller or not. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 937: Lidd Controller
This is set up and activated in a similar manner to the write function described above. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 938: Lidd I/O Name Map
Synchronous Clock (optional) The timing parameters are defined by the LIDD_CS0_CONF and LIDD_CS1_CONF registers, which are described in Section 23.3.5. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 939: Operation Modes Supported By Raster Controller
LCD_PCLK Pixel clock LCD_HSYNC Horizontal clock(Line Clock) LCD_VSYNC Vertical clock (Frame Clock) LCD_AC_ENB_CS Output enable LCD_MCLK Not used SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 940: Logical Data Path For Raster Controller
Their operation and programming techniques are covered in detail. The output format is also described in Section 23.2.5.5. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 941: Frame Buffer Structure
(in the same format as palette entry). For STN565, see the 16 BPP STN mode bit (Section 23.3.8.8). SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 942: 16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 Bpp)
Palette Entry 15 Base + 1Eh A. Bits-per-pixels (BPP) is only contained within the first palette entry (palette entry 0). Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 943: 256-Entry Palette/Buffer Format (8 Bpp)
Figure 23-7. 16-BPP Data Memory Organization (TFT Mode Only)—Little Endian 16 bits/pixel Bit 15 Base Pixel 0 Base + 2 Pixel 1 SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 944: 12-Bpp Data Memory Organization-Little Endian
Pixel 0 Pixel 1 Base + 1 Pixel 2 Pixel 3 Base + 2 Pixel 4 Pixel 5 Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 945: 2-Bpp Data Memory Organization
23.2.5.4.2 Active (TFT) Mode The gray-scaler/serializer is bypassed. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 946: Color/Grayscale Intensities And Modulation Rates
15 grayscales, but exists anyway 3375 possible colors 4096 possible colors 3375 possible colors (STN_565 = 1) Up to 65536 possible colors Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 947: Monochrome And Color Output
(Pix8) Pixel data pin 1 (Pix3) (Pix5) (Pix8) Pixel data pin 0 (Pix3) (Pix6) (Pix9) Pixel clock Color SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 948: Raster Mode Display Format
1, L-1 2, L-1 P, L-1 1, L 2, L 3, L P-2, L P-1, L P, L Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 949: Lcd Revision Identification Register (Revid)
Table 23-10. LCD Revision Identification Register (REVID) Field Descriptions Field Value Description 31-0 4C10 0100h Peripheral Identification Number SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 950: Lcd Control Register (Lcd_Ctrl)
CLKDIV value to yield a target pixel clock frequency can be calculated using the following equation: LCD_CLK LCD_PCLK + CLKDIV Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 951: Pixel Clock Frequency Programming Limitations
4 (4 pixel) STN monochrome(8 output lines per panel) 8 (8 pixel) STN color 8 (2 2/3 pixel) SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 952: Lcd Status Register (Lcd_Stat)
Raster or LIDD Frame Done (shared; depends on whether Raster or LIDD mode enabled) Raster or DMA_to_LIDD engine is enabled Raster or DMA_to_LIDD disabled and the active frame has just completed Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 953 FUF = 1 when the dithering logic is not supplying data to the FIFO at a sufficient rate. • FUF = 0 as long as FIFO has not underrun. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 954 (PL = 01) mode, LCD must be turned off in order to reset/clear the interrupt. But in this particular mode, make sure not to turn off the LCD before getting the loading interrupt. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 955: Lcd Lidd Control Register (Lidd_Ctrl)
Do Not Invert Read Strobe/Enable Invert Read Strobe/Enable Read Strobe is active low by default; Enable is active high by default SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 956 100b LCD_PCLK LCD_HSYNC LCD_VSYNC LCD_AC_ENB_CS LCD_MCLK Sync MPU68 Async MPU68 Sync MPU80 Async MPU80 Hitachi (Async) 5h-7h Reserved Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 957: Lcd Lidd Csn Configuration Register (Lidd_Csn_Conf)
CS0 device access unless the two accesses are both reads, in which case this delay is not incurred. CS_DELAY = ROUNDUP(7/CLKDIV) + TA SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 958: Lcd Lidd Csn Address Read/Write Register (Lidd_Csn_Addr)
Peripheral Device Address/Index value. On writes this field is loaded into the CS0 peripheral device's address generator On reads this field contains the CS0 peripheral device's status. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 959: Lcd Lidd Csn Data Read/Write Register (Lidd_Csn_Data)
Peripheral Device Data value. On writes this field is loaded into the CS0 peripheral device On reads this field contains the CS0 peripheral device's data. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 960: Lcd Raster Control Register (Raster_Ctrl)
DMA request should be disabled. The delay clock count starts after 16 words are loaded into the input FIFO. Delay Time = [(LCD Pixel Clock) × FIFO_DMA_DELAY] 11-10 Reserved Reserved Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 961 Enable Monochrome display operation. RASTER_EN LCD Raster Controller Enable Disable the LCD Raster controller. Enable the LCD Raster controller. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 962: Lcd Controller Data Pin Utilization For Mono/Color Passive/Active Panels
Pixel data[11:0] or Pixel data[15:0] according to TFT_ALT_MAP bit in the LCD Raster Control Register (RASTER_CTRL) Color 16 Active Pixel data[15:0] Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 963: Monochrome Passive Mode Pixel Clock And Data Pin Timing
2 and 2/3 pixel 2 and 2/3 pixel 2 and 2/3 pixel 2 and 2/3 pixel LCD_D[x:0] LCD_HSYNC LCD_VSYNC SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 964: Active Mode Pixel Clock And Data Pin Timing
FIFO underflow during palette loading phase. When FDD = 00h, the FIFO DMA request delay function is disabled. This function is only used for palette loading. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 965: Tft Alternate Signal Mapping Output
When TFT_ALT_MAP = 0, the four red, four green, and four blue data are right-aligned on pixel data [11- 0]. The upper pixel data [15-12] are cleared to 0. There is no duplication. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 966: 12-Bit Stn Data In Frame Buffer
Red bit 11, green bits 6, 5 and blue bit 0 are not used as image data and are ignored. The 16-bit STN resolution is equal to the 12-bit STN resolution (3375 colors) Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 967: Lcd Raster Timing Register 0 (Raster_Timing_0)
16-1024. PPL is used to count the correct number of pixel clocks that must occur before the line clock can be pulsed. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 968 HBP generates a wait period ranging from 1–256 pixel clock cycles (program to value required minus 1). Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 969: Lcd Raster Timing Register 1 (Raster_Timing_1)
10-bit value, which represents between 1–1024 lines per panel. LPP is used to count the correct number of line clocks that must occur before the frame clock can be pulsed. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 970: Vertical Synchronization Pulse Width (Vsw) - Active Mode
Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 971: Vertical Front Porch (Vfp)
(LCD_HSYNC) Pixel Clock HFP = 2 (LCD_PCLK) Line 479 Data Line 0 Data Data (LCD_D[x:0]) LPP = 480 SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 972: Vertical Back Porch (Vbp)
VFP = 2 HSW = 6 Line 0 Data Line 1 Data Line 2 Data Data (LCD_D[x:0]) PPL = 17 Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 973: Lcd Raster Timing Register 2 (Raster_Timing_2)
AC bias interrupt status is cleared. A value of zero will not produce an interrupt. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 974 When IPC = 0, data is driven onto the LCD data lines on the rising edge of the pixel clock. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 975: Sync_Ctrl = 0, Ipc = 1 In Tft Mode
Figure 23-36. SYNC_CTRL = 0, IPC = 1 in TFT Mode IPC = 1 LCD_PCLK Pixel 0 LCD_D[x:0] LCD_HSYNC LCD_VSYNC LCD_AC_ENB_CS SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 976: Sync_Ctrl = 1, Sync_Edge = 0, And Ipc = 1
When SYNC_CTRL = 0, HSYNC and VSYNC are driven on opposite edges of the pixel clock from pixel data. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 977: Lcd Raster Subpanel Display Register (Raster_Subpanel)
DPD value when HOLS = 1, but on one filled with video data when HOLS = 0 (see Figure 23-39 Figure 23-40). SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 978: Subpanel Display: Spen = 1, Hols = 1
• When HOLS = 0: normal panel (whole panel is filled with video data from the frame buffer). Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 979: Lcd Dma Control Register (Lcddma_Ctrl)
One frame buffer (FB0 only) used. Two frame buffers used; DMA ping-pongs between FB0 and FB1 in this mode. SPRUH91D – March 2013 – Revised September 2016 Liquid Crystal Display Controller (LCDC) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 980: Lcd Dma Frame Buffer N Base Address Register (Lcddma_Fbn_Base)
31-0 FBn_CEIL 0-FFFF FFFFh Frame Buffer n Ceiling Address pointer. Note: The 2 LSBs are hardwired to 00b. Liquid Crystal Display Controller (LCDC) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 981: Multichannel Audio Serial Port (Mcasp)
This chapter describes the multichannel audio serial port (McASP). See your device-specific data manual to determine how many McASPs are available on your device..........................Topic Page ....................... 24.1 Registers 1036 SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 982: Features
– Independent Read FIFO and Write FIFO – 256 bytes of RAM for each FIFO (read and write) Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 983: Protocols Supported
(note that the internal bit clock for DIT runs two times faster than the equivalent bit clock for I2S mode, due to the need to generate Biphase Mark Encoded Data). SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 984: Mcasp Block Diagram
McASP2 has up to 4 serial data pins, n = 3. One of the DSP's external pins, see your device-specific data manual. Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 985: Mcasp To Parallel 2-Channel Dacs
Figure 24-3. McASP to 6-Channel DAC and 2-Channel DAC player Coaxial/ optical On chip S/PDIF encoded Stereo McASP 6-ch 2-ch SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 986: Mcasp To Digital Amplifier
Stereo I2S On chip LF, RF 2-ch ADC McASP C, LFE S/PDIF 2-ch ADC encoded LS, RS 2-ch ADC Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 987: Tdm Format-6 Channel Tdm Example
Slot 3 TDM frame FS duration of slot is shown. FS duration of single bit is also supported. SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 988: Tdm Format Bit Delays From Frame Sync
Word n Word n+1 right channel left channel right channel 1 to 16 data pins may be supported. Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 989: Biphase-Mark Code (Bmc)
0 1 0 0 1 0 1 0 Cell Table 24-1. Biphase-Mark Encoder Previous State at Pin Data (Unencoded) AXR[n] BMC-Encoded Cell Output at AXR[n] SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 990: S/Pdif Subframe Format
DIT mode. If an underrun condition occurs, the DIT resynchronizes to the correct logic level on the AXR[n] pin before continuing with the next transmission. Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 991: S/Pdif Frame Format
Figure 24-11. S/PDIF Frame Format Channel Channel Channel Channel Channel Channel Subframe 1 Subframe 2 Frame 191 Frame 1 Frame 0 SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 992: Definition Of Bit, Word, And Slot
(2) P - pad bits. Bits b7 to b0, together with the four pad bits, form a slot. (3) In this example, the data is transmitted MSB first, left aligned. Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 993: Bit Order And Word Alignment Within A Slot Examples
LSB first, pad with bit 4 8-bit word 12-bit slot Unshaded: bit belongs to word Shaded: bit is a pad bit SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 994: Definition Of Frame And Frame Sync Width
For TDM format, the term time slot is interchangeable with the term slot defined in this section. For DIT format, a Time Slot McASP time slot corresponds to a DIT subframe. Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 995: Overview
In DIT mode, it is possible to use only internally-generated clocks and frame syncs. SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 996: Transmit Clock Generator Block Diagram
(internal/external) (ACLKXCTL.5) Divider /1... /32 CLKXDIV AHCLKX (ACLKXCTL[4−0]) HCLKXP (AHCLKXCTL.14) HCLKXM (AHCLKXCTL.15) Divider /1... /4096 AUXCLK HCLKXDIV (AHLKXCTL[11−0]) Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 997: Receive Clock Generator Block Diagram
(polarity) (internal/external) (AHCLKRCTL.14) (AHCLKRCTL.15) ACLKR RCLK CLKRM ASYNC (internal/external) (ACLKXCTL.6) XCLK (ACLKRCTL.5) CLKRP (from Figure 15) (polarity) (ACLKRCTL.7) SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 998: Frame Sync Generator Block Diagram
AFSX FSXM FSRP (internal/ (AFSRCTL.0) external) (AFSXCTL.1) Internal frame sync AFSR FSRP FSRM (AFSRCTL.0) (internal/external) (AFSRCTL.1) ASYNC (ACLKXCTL.6) Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 999: Individual Serializer And Connections Within Mcasp
In DIT mode, in addition to the data, the serializer shifts out other DIT-specific information accordingly (preamble, user data, etc.). The serializer configuration is controlled by SRCTL[n]. SPRUH91D – March 2013 – Revised September 2016 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...
Page 1000: Receive Format Unit
Programmable rotate by: RROT 0, 4, 8, 12, 16, 20, 24, 28 Bit reverse RRVRS Parallel read from XRBUF[n] 1000 Multichannel Audio Serial Port (McASP) SPRUH91D – March 2013 – Revised September 2016 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated...

This manual is also suitable for:

Tms320c6747 dsp

Texas Instruments TMS320C6745 DSP Reference Manual

Preface

2 DSP Subsystem

4 System Memory

5 Memory Protection Unit (MPU)

6 Device Clocking

7 Phase-Locked Loop Controller (PLLC)

8 Power and Sleep Controller (PSC)

9 Power Management

10 System Configuration (SYSCFG) Module

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Summary of Contents for Texas Instruments TMS320C6745 DSP