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System Clock Generator
The system clock generator function generates and distributes all of the
clocks required for normal system operation. The clock generator for the
processor, memory, and PCI devices is designed in such a manner as to
maintain the strict edge to edge jitter and low clock to clock skew required
by these devices.
Additional clocks that may be required should be generated near the
individual devices requiring clocks to minimize onboard trace lengths.
Flash Memory
The MVME2100 contains two banks of Flash memory accessed via the
integrated memory controller contained within the processor. Bank B
consists of two 32-pin PLCC sockets that can be populated with up to
1024KB of Flash memory, and resides at address 0xFFF00000, and is
restricted to 8 bits in width.
Bank A may be populated with four 512Kx16 Flash devices to obtain 4MB
of 64-bit wide expansion Flash memory or four 1Mx16 Flash devices to
obtain 8MB of 64-bit wide Flash memory. The expansion Flash memory
starts at address 0xFF000000.
System Memory
System memory for the MVME2100 is provided by 2 banks of
synchronous DRAM. Each bank consists of five 4Mx16 SDRAM devices
providing a 32MB bank organized in a 4Mx72 configuration. This allows
memory configurations of 32 or 64MB that can be supported by the board.
During system initialization, the firmware determines the presence, and
configuration of each memory bank installed by reading the contents of the
serial presence detect ROM located on the board. The system firmware
then initializes the MPC8240 memory controller for proper operation
based on the contents of the serial presence detection ROM.
http://www.motorola.com/computer/literature
Functional Description
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