S.vlmt2 Variation Rate Limiter 2 - Mitsubishi MELSEC-Q series Programming Manual

9.19 S.VLMT2 Variation Rate Limiter 2
9.19
S.VLMT2
S.VLMT2
Structured ladder/FBD
S_VLMT2
EN
s1
s2
Input argument EN
S1
S2
Output argument ENO
D1
D2
Internal devices
Setting
data
Bit Word
––
S1
––
D1
––
S2
––
D2
*1 Special register SD1506 can be specified as a dummy device.
Function
Limits the varying speed of the output value.
E1(BW)
BB1
BB2
Ladder diagram
Start contact
ENO
d1
d2
: Execution condition
: Input data start device
: Operation constant start device
: Execution result
: Block memory start device
*1
: Dummy device
J \
R, ZR
Bit
S.VLMT2 S1 D1
Structured text language
ENO:=S_VLMT2(EN,s1,s2,d1,d2);
: Bit
: Real data type
: Array of real data type (0..3)
: Bit
: Array of any 16-bit data (0..2)
: Real data type
U \G
Word
––
––
––
––
S.VLMT2
S2 D2
Zn Constant Other
Input value E1
Output value BW
171
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