Mitsubishi MELSEC-Q series Programming Manual page 145

Set Data
Block diagram
The processing block diagram of the S.PHPL instruction is shown below.
(The numerals (1) to (5) in the diagram indicate the order of the processing.)
RL, RH
E1
Upper limit alarm
Lower limit alarm
Upper upper limit alarm
Lower lower limit alarm
RUN(SPA 0)
(5)
Loop stop
STOP(SPA 1)
judgment
SPA
(5)
ERRI PHI
ERRI PLI
ERRI HHI
ERRI LLI
ERRI DPPI
ERRI DPNI
PHA
PLA
HHA
LLA
DPPA
DPNA
LL HH PL PH
(1)
Engineering value reverse conversion
LL' HH' PL' PH'
(2)
Upper/lower limit check
BW
Loop stop
OFF
processing
HS DPL, CTIM
(4)
(3)
Change rate
check
Positive
Negative
AND
AND
AND
AND
AND
AND
S.PHPL
PV
Engineering
value
conversion
BW
BB2
BB3
BB4
BB5
BB1
OR
143
9
2
3
4
4
6
7
8