Mitsubishi MELSEC-Q series Programming Manual page 148

S.PHPL
(2) Upper/lower limit check
The upper/lower limit checks of the input value (E1) are made under the following conditions.
Check item
Upper limit check
Lower limit check
Upper Upper limit check
Lower lower limit check
*1 When PHI or ERRI in the alarm detection inhibition (INH) is set to 1, PHA and BB2 show 0 since the alarm is prohibited.
*2 When PLI or ERRI in the alarm detection inhibition (INH) is set to 1, PLA and BB3 show 0 since the alarm is prohibited.
*3 When HHI or ERRI in the alarm detection inhibition (INH) is set to 1, HHA show 0 since the alarm is prohibited.
*4 When LLI or ERRI in the alarm detection inhibition (INH) is set to 1, LLA show 0 since the alarm is prohibited.
(3) Change rate check
(a) A change rate check is performed for the time specified in CTIM.
The number of change rate checks to be made is found by the following expression.
CTIM
m
T
m varies from 1 to m.
However, when m = 0 (integer part), no processing is performed.
For example, when m = 4, the processing is performed as shown below.
(a) Zero time E1
(b) One time E1
(c) Two time E1
(d) Three time E1
(e) Four time E1
(b) The change of the input data is compared with the change rate alarm value (DPL) in each execution cycle ( T).
Check item
Change rate check
*1 When DPPI or ERRI in the alarm detection inhibition (INH) is set to 1, DPPA and BB4 show 0 since the alarm is prohibited.
*2 When DPNI or ERRI in the alarm detection inhibition (INH) is set to 1, DPNA and BB5 show 0 since the alarm is prohibited.
146
Condition
*1
E1 > PH'
PHA = 1
E1  PH' - HS
PHA = 0
Others
PHA: Last value is status hold
*2
E1 < PL'
PLA = 1
E1  PL' + HS
PLA = 0
Others
PLA: Last value is status hold
*3
E1 > HH'
HHA = 1
E1  HH' - HS
HHA = 0
Others
HHA: Last value is status hold
*4
E1 < LL'
LLA = 1
E1  LL' + HS
LLA = 0
Others
LLA: Last value is status hold
E1
n
n-4
E1
n+1 n
DPL
E1
n+2 n
E1
n+3 n
E1
n+4 n
Condition
 DPL
E1 - E1
DPPA = 1
n+m n
DPPA = 0
Others
 - DPL
E1 - E1
DPNA = 1
n+m n
Others DPNA = 0
ALM
*1
Hold
*2
*3
*4
E1 E1
n n
1 2
E1
n
3
E1
E1
n
a b c d e
Execution cycle
CTIM
ALM BB4
*1 *1
1
0
*2
––
––
BB2 BB3
*1
––
1
0 ––
*1
––
*2
––
1
–– 0
*2
––
Hold
–– ––
–– ––
–– ––
–– ––
–– ––
–– ––
n
4
t
BB5
––
––
*2
1
0