Mitsubishi MELSEC-Q series Programming Manual page 143

(2) Change rate limiter
In the change rate limiter, the following operation is performed and the result of the operation is stored into the current
rate value (Rn).
Condition
)  DR
(SPR - R
n
)  - DR
(SPR - R
n
|SPR - R | < DR
n
(3) Rate operation
Rate operation is performed with the following operation expression.
R RMIN
n
BW E1
RMAX RMIN
(4) Loop stop processing
(a) Setting 1 in SPA of the alarm detection (ALM) selects a loop stop.
A loop stop performs the following processing and terminates the S.R instruction.
1) BW retains the last value.
2) The operation mode (MODE) is changed to MAN.
(b) Setting 0 in SPA of the alarm detection (ALM) selects a loop run.
A loop run performs "(5) Control cycle judgment".
(5) Control cycle judgment
(a) When the specified control cycle is not reached, BW is retained and the S.R instruction is terminated.
(b) When the specified control cycle is reached, "(6) Mode judgment" is performed.
(6) Mode judgment
Either of the following processings is performed depending on the operation mode (MODE) setting.
(a) When the operation mode (MODE) is any of CAS, CCB and CSV
1) When the set value (E2) is specified, engineering value conversion is made with the following expression and
then "(2) Change rate limiter" is performed.
RMAX
SPR
100
2) When the set value (E2) is not specified, "(2) Change rate limiter" is performed without engineering value
conversion being made.
(b) When the operation mode (MODE) is any of MAN, AUT, CMV, CMB, CAB, LCM, LCA and LCC, "(1) Tracking
processing" is executed.
Operation Error
In the following cases, the error flag (SM0) turns ON and the error code is stored in SD0.
Error code
When an operation error occurs
When the values of
4100
normalized number
When CT < 0 or the execution cycle (SD1500) < 0
When the values of
4140
normalized number
4141 When an operation error occurs
Operation expression
R = R + DR
n n-1
R = R - DR
n n-1
R = SPR
n
BIAS
RMIN
RMIN
E2
Error definition
, are either a non-numeric or non-
S1 D2
, are either a non-numeric or non-
S1 D2
QnPHCPU QnPRHCPU
–– ––
–– ––
S.R
9
2
3
4
4
6
7
8
QnUDPVCPU
––
––
141