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Falcon ECC Memory Controller Chipset
3
Error_Address Register
ADDRESS
BIT
NAME
OPERATION
RESET
3-44
esblk0,esblk1
Together these two bits indicate which block of
DRAM was being accessed when their Falcon logged a
scrub error. esblk0,esblk1 are 0,0 for Block A; 0,1 for
Block B; 1,0 for Block C; and 1,1 for Block D.
scof
scof is set by its SBE COUNT register rolling over from
$FF to $00. It is cleared by software writing a 1 to it.
SBE COUNT This register keeps track of the number of single-bit
errors that have occurred since it was last cleared. It
counts up by one each time its half of the Falcon pair
detects a single-bit error (independent of the state of the
elog bit). It is cleared by power-up reset and by software
writing all zeros to it. When SBE COUNT rolls over from
$FF to $00, its Falcon sets the scof bit. It also pulses the
INT_ signal low if the scien bit is set.
ERROR_ADDRESS
READ ONLY
ERROR_ADDRESS
to bits 0-27 of the PowerPC 60x address bus when their
Falcon last logged an error during a PowerPC access to
DRAM. They reflect the value of the DRAM row and
column addresses if the error was logged during a scrub
cycle. In this case, bits 2-14 correspond to row address
signals 0-12 respectively and bits 15-27 correspond to
column address signals 0-12 respectively. Refer to
3-18 on page 3-59
the section on
PowerPC addresses correspond to DRAM row and
column addresses.
$FEF80038
X P
These bits reflect the value that corresponds
in the subsection on
Software
Considerations. It shows how
Computer Group Literature Center Web Site
Table
Sizing DRAM
in
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