Panasonic FP2 -C1A Manual page 88

Sample Program of Analog Input Offset Setting
11.1 Sample Program (CPU Unit with Analog I/O)
Sample program:
R 9013
F0 MV
Initial
setting
F151 WRT K 0
Specifies the CPU unit with
analog I/O in slot no. 0.
The 1 - word data from data register DT 0
is written to the shared memory address 16.
R 9013
F0 MV
Initial
setting
F0 MV
F0 MV
F151 WRT
Specifies the CPU unit with analog
I/O in slot no. 0.
The 3 - word contents of data register DT 10 to DT12
is written to the shared memory addressees 30 to 32.
R 0
F0 MV
ch 0
preparation
completion
R 1
F0 MV
ch 1
preparation
completion
R 2
F0 MV
ch 2
preparation
completion
R 9010
F150 READ K 0
Always on
Specifies the CPU unit with analog
I/O in slot no. 0.
The 1 - word data from shared memory address 10
11 - 4
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, H 111 , DT 0
ch 0 to 2
execution
, , DT 0 , K 1 K 16 ,
ch 0 to 2
execution
, K 0 , DT 10
ch 0 offset
, K 10 , DT 11
ch 1 offset
, K 20 , DT 12
ch 2 offset
, K 0 , DT 10 , K 3 K 30 ,
ch 0 to 2
offset
, WX 0 , DT 100
ch 0 Input
value
, WX 1 , DT 101
ch 1 Input
value
, WX 2 , DT 102
ch 2 Input
value
, , K 10 K 1 , , WR 0
Preparation
completion
flag area
is read to the internal relay WR0.
Execution of conversion
processing setting for ch
0 to ch 2 analog inputs
Analog input offset setting
ch 0: K0
ch 1: K10
ch 2: K20
Analog input Reading
Preparation completion flag
for analog input
Reading
ED
FP2 Analog Unit