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Technical Description
Length of the Shift Register
The total length of the shift register is obtained from the sum of the data bits of all plugged-in
modules and of the empty slots. The check bit is not counted.
You must know the length of the shift register to be able to determine the data cycle time. Data
cycle time is 25 µs x number of data bits.
Table 2-2. Number of Bits per Module in the Shift Register
Diagnostic module or vacant slot
4-channel digital input and output modules
500 Hz comparator module, 500 Hz timer module,
500 Hz counter module
25 KHz counter module
8-channel digital input and output modules
Digital input and output module, 16 inputs/16 outputs
Simulator module
Analog modules for each activated channel
CP 521, IP 262, IP 266, IP 267
Refer to the individual manuals for information on other modules.
*
This does not apply to the 466-8MC11 analog input module (8 data bits).
The CPU specifies the maximum length of the shift register in a particular configuration.
•
CPU 100:
256 data bits, 128 (max.) of these from analog modules
•
CPU 102:
480 data bits, 256 (max.) of these from analog modules
•
CPU 103:
704 data bits, 512 (max.) of these from analog modules
Note
If the maximum expansion allowed is exceeded, the S5-100U goes into the STOP mode.
The "PEU" bit (I/O not ready) is set in the ISTACK.
2-8
Plugged-in Module
S5-100U
Number of Data Bits
4
4
4
32
8
16
8
16*
64
EWA 4NEB 812 6120-02
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