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Electrical Specifications
5.6.2 Layout Considerations
Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout
practices should always be observed when planning trace routing to the discrete components used in the
oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close
to the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible
after routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should
be run between these two signal lines. This also helps to minimize stray capacitance between these two
signals.
5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or
four to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock
mode register. The contents of this field only affect clock generation while the device is in bypass mode. In
this mode, the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−3 and Table 5−4 assume testing over recommended operating conditions and H = 0.5t
Figure 5−3).
NO.
C1
t c(CI)
Cycle time, X2/CLKIN
C2
t f(CI)
Fall time, X2/CLKIN
C3
t r(CI)
Rise time, X2/CLKIN
C10
t w(CIL)
Pulse duration, CLKIN low
C11
t w(CIH)
Pulse duration, CLKIN high
† This device utilizes a fully static design and therefore can operate with t c(CI) approaching ∞. If an external crystal is used, the X2/CLKIN cycle
time is limited by the crystal frequency range listed in Table 5−2.
NO.
C4
t c(CO)
Cycle time, CLKOUT
C5
t d(CIH-CO)
Delay time, X2/CLKIN high to CLKOUT high/low
C6
t f(CO)
Fall time, CLKOUT
C7
t r(CO)
Rise time, CLKOUT
C8
t w(COL)
Pulse duration, CLKOUT low
C9
t w(COH)
Pulse duration, CLKOUT high
† This device utilizes a fully static design and therefore can operate with t c(CO) approaching ∞. If an external crystal is used, the X2/CLKIN cycle
time is limited by the crystal frequency range listed in Table 5−2.
‡ It is recommended that the DPLL synthesised clocking option be used to obtain maximum operating frequency.
§ D = 1/(PLL Bypass Divider)
78
SPRS163H
Table 5−3. CLKIN Timing Requirements
Table 5−4. CLKOUT Switching Characteristics
PARAMETER
(see
c(CO)
MIN
MAX
UNIT
400 †
20
ns
4
ns
4
ns
6
ns
6
ns
MIN
TYP
MAX
UNIT
20 ‡
D*t c(CI) §
1600 †
ns
10
20
30
ns
1
ns
1
ns
H−2
H+2
ns
H−2
H+2
ns
April 2001 − Revised January 2008
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