Low Dio Power-Up State (Pxi-6508, Pci-6503 Only); Figure 3-6. Dio Channel Configured For Low Dio Power-Up State With External Load - National Instruments PCI-DIO-96 User Manual

Chapter 3 Signal Connections

Low DIO Power-up State (PXI-6508, PCI-6503 Only)

PCI-DIO-96/PXI-6508/PCI-6503 User Manual
If you select pulled-low mode, each DIO line will be pulled to GND
(0 VDC) using a 100 kΩ resistor. If you want to pull a specific line high,
connect a pull-up resistor that will give you a minimum of 2.8 VDC. The
DIO lines are capable of sinking a maximum of 2.5 mA at 0.4 V in the low
state. Using the largest possible resistance value ensures that you do not use
more current than necessary to perform the pull-up task.
Also, ensure the pull-up resistor value is not so large that leakage current
from the DIO line along with the current from the 100 kΩ pull-down
resistor brings the voltage at the resistor below a TTL high level of
2.8 VDC.
DIO Board
82C55

Figure 3-6. DIO Channel Configured for Low DIO Power-up State with External Load

Example:
Set jumper W1 to low, which means all DIO lines are pulled low at power
up. To pull one channel high, complete the following steps:
1. Install a load (R
L
greater the current consumption and the higher the voltage.
2. Using the following formula, calculate the largest possible load to
maintain a logic high level of 2.8 V and supply the maximum sink
current:
 R
V = I × R
L L
where V = 2.2 V; Voltage across R
I = 28 μA + 10 μA; 2.8 V across the 100 kΩ pull-up resistor
and 10 μA maximum leakage current (except lines PC0 and
PC3)
= 5.7 kΩ; 2.2 V/38 μA
therefore R
L
+5 V
R
100 kΩ
GND
). Remember that the smaller the resistance, the
= V/I
L
3-12
L
Digital I/O Line
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