National Instruments PCI-DIO-96 User Manual page 52

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Appendix B
CIRQ1 PPI C Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI C sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI C does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.
CIRQ0 PPI C Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI C sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI C does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.
BIRQ1 PPI B Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI B sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI B does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.
BIRQ0 PPI B Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI B sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI B does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.
AIRQ1 PPI A Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI A sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI A does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.
AIRQ0 PPI A Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI A sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI A does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.
Register-Level Programming — Interrupt Control Register 1
B-11 PCI-DIO-96/PXI-6508/PCI-6503 User Manual