Timing Specifications; Table 4-2. Signal Names Used In Timing Diagrams - National Instruments PCI-DIO-96 User Manual

Chapter 4 Theory of Operation

Timing Specifications

Name Type
STB* Input
IBF Output
ACK* Input
OBF* Output
INTR Output
RD* Internal
WR* Internal
DATA Bidirectional
PCI-DIO-96/PXI-6508/PCI-6503 User Manual
This section lists the timing specifications for handshaking with your DIO
board. The handshaking lines STB* and IBF synchronize input transfers.
The handshaking lines OBF* and ACK* synchronize output transfers.
Table 4-2 describes signals appearing in the handshaking diagrams.

Table 4-2. Signal Names Used in Timing Diagrams

Strobe Input—A low signal on this handshaking line loads data into
the input latch.
Input Buffer Full—A high signal on this handshaking line indicates
that data has been loaded into the input latch. A low signal indicates
the board is ready for more data. This is an input acknowledge
signal.
Acknowledge Input—A low signal on this handshaking line
indicates that the data written to the port has been accepted. This
signal is a response from the external device indicating that it has
received the data from your DIO board.
Output Buffer Full—A low signal on this handshaking line
indicates that data has been written to the port.
Interrupt Request—This signal becomes high when the 82C55A
requests service during a data transfer. The appropriate interrupt
enable bits must be set to generate this signal.
Read—This signal is the read signal generated from the control
lines of the computer I/O expansion bus.
Write—This signal is the write signal generated from the control
lines of the computer I/O expansion bus.
Data Lines at the Specified Port—For output mode, this signal
indicates the availability of data on the data line. For input mode,
this signal indicates when the data on the data lines should be valid.
Description
4-4 ni.com