Low Dio Power-Up State; Figure 3-4. Dio Channel Configured For Low Dio Power-Up State With External Load - National Instruments PC-DIO-24/PnP User Manual

Low DIO Power-up State

© National Instruments Corporation
If you select pulled-low mode, each DIO line will be pulled to GND
(0 VDC) using a 100 k
a pull-up resistor that will give you a minimum of 2.8 VDC. Using the
largest possible resistance value ensures that you do not to use more
current than necessary to perform the pull-up task, and that the DIO can
still drive the line. The DIO lines are capable of sinking a maximum of
2.5 mA at 0.4 V in the low state.
Also, make sure the pull-up resistor value is not so large that leakage
current from the DIO line along with the current from the 100 k
pull-down resistor brings the voltage at the resistor below a TTL high
level of 2.8 VDC.
PC-DIO-24/PnP
82C55A

Figure 3-4. DIO Channel Configured for Low DIO Power-up State with External Load

Example:
At power up, the board is configured for input and jumper W1 is set in
the low DIO power-up state, which means all DIO lines are pulled low.
If you want to pull one channel high, follow these steps:
1. Install a load (R
L
greater the current consumption and the higher the voltage.
2. Using the following formula, calculate the largest possible load to
maintain a logic high level of 2.8 V and supply the maximum sink
current.
V = I * R
L
V = 2.2 V
I = 28 A + 11 A
resistor. To pull a specific line high, connect
+5 V
R
100 k
GND
). Remember that the smaller the resistance, the
R = V / I, where:
L
; voltage across R
; 2.8 V across the 100 k
resistor and 11 A max leakage
current
3-9
Chapter 3 Signal Connections
L
Digital I/O Line
L
PC-DIO-24/PnP User Manual
pull-up