Figure 3-5. Dio Channel Configured For High Dio Power-Up State With External Load - National Instruments PCI-DIO-96 User Manual

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However, ensure the resistor value is not so large that leakage current from
the DIO line along with the current from the 100 kΩ pull-up resistor drives
the voltage at the resistor above a TTL low level of 0.4 VDC.
DIO Board
82C55

Figure 3-5. DIO Channel Configured for High DIO Power-up State with External Load

Example:
By default, all DIO lines are pulled high at power up. To pull one channel
low, complete the following steps:
1. Install a load (R
L
greater the current consumption and the lower the voltage.
2. Using the following formula, calculate the largest possible load to
maintain a logic low level of 0.4 V and supply the maximum driving
current:
 R
V = I × R
L L
where V = 0.4 V; Voltage across R
I = 46 μA + 10 μA; 4.6 V across the 100 kΩ pull-up resistor
and 10 μA maximum leakage current(except lines PC0 and
PC3)
= 7.1 kΩ; 0.4 V/56 μA
therefore R
L
This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO line
at power up. You can substitute smaller resistor values to lower the voltage
or to provide a margin for V
smaller values draw more current, leaving less drive current for other
circuitry connected to this line. The 7.1 kΩ resistor reduces the amount of
logic high source current by 0.4 mA with a 2.8 V output.
The maximum leakage current on most lines is 10 μA. The maximum
leakage current on the PC(0) and PC(3) lines is 20 μA.
+5 V
100 kΩ
R
GND
). Remember that the smaller the resistance, the
= V/I,
L
variations and other factors. However,
cc
3-11 PCI-DIO-96/PXI-6508/PCI-6503 User Manual
Chapter 3 Signal Connections
Digital I/O Line
L