IBM Series 1 User Manual page 53
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4.
5.
A
second system reset is activated.
The time from the
deactivation of initiate
IPL
and
activation
of
the
second system reset. CT3, is 200 nanoseconds minimum as
seen at the device interface.
This second system reset
is of a unique nature.
The IPL source device maintains
an active IPL tag while
using
this
system
reset
to
enable
the
cycle steal transfer for the storage load.
The device should use only the
trailing
edge
of
the
second system reset to accomplish this enabling.
The
second
system
reset
is
deactivated.
IPL cycle
steal requests and transfers
may
then begin.
The time.
T3,
from the deactivation of the second system reset to
the activation of the first cycle steal request must be
greater than zero as seen at the device interface.
The
maximum time is device dependent.
This time should
be
kept
to
a
reasonable
minimum
so
that
the
IPL is
completed in a reasonable time and
the
operator
does
not
suspect
that
the system is inoperative.
At this
time, the function of the status
bus
returns
to
its
original
function;
that
is,
the reporting of status
information to the I/O device being serviced.
The
IPL
record
length
can
be
up
to
a
maximum
of
64KB.
Successful
completion
of
IPL
is
signalled
to
the
processor by the device dropping the IPL tag.
Time T4,
from the end of cycle steal requests
dnd
transfers
(as
defined
by
the
deactivation of the last service gate
return)
to the
deactivation
of
the
IPL
tag
has
a
mln1mum
time
of
zero.
The
maximum
time is device
dependent, but should also be kept to a minimum for the
same reason as stated tor time T3.
Following the successful completion of IPL and the
dropping
of
the
IPL
tag,
the
I/O
device
must be
prepared to level zero with its I-bit on and presenting
an interrupt request to the processor I/O channel.
The
device must be available in all other
respects.
When
the
interrupt
is
accepted,
the
device presents the
device end interrupt condition code.
6.
If a system reset occurs after the device
has
enabled
cycle
steal
requests
and
transfers, the device must
deactivate the IPL tag within 200
nanoseconds
at
the
device
interface, terminate the cycle steal transfers,
and execute all other
system
reset
functions.
Note
that
this
system reset could be the result of
(l)
the
operator pressing the reset key, or
(2)
the
operator
pressing
the
load
key
to
begin
another
processor
initiated IPL sequence where the system reset leads the
initiate
1PL
tag at the device interface.
Therefore,
this represents an added condition
for
resetting
the
1PL
tag.
Note
also that this condition is dependent
upon being in an enabled state for 1PL
tr.ansfer
as
a
result of the second system reset.
2-38
GA34-0033
('~
f
"
,
,
c
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