IBM Series 1 User Manual page 37

The activation of address bus bit 16 causes all I/O
attachments to compare address bus bit 8--15 (the device
address) with the attachment's assigned device addressees).
An equal comparison constitutes DPe selection of the device.
Upon selection, the device examines the command in address
bus bits 00--07, (also the data bus on write sequences for
proper parity), and applicable device internal conditions
necessary for determining command acceptance and I/O
instruction condition code reporting. No specific device
action or state change must occur as a result of the
selection and examination of conditions relative to the
command itself until a) address gate is recognized by the
selected device for write sequences, or b) data strobe is
recognized by the selected device for read sequences. For
write sequences, it is preferrable for the device not to
change state until data strobe is recognized, except during
execution of a Device Reset command. If an I/O device has
an interrupt request active on the interface and executes a
device reset or prepare command, the device, as appropriate,
drops its request or alters its requested level prior to the
deactivation of data strobe as seen at the device interface.
2.
2-22
Address gate is deskewed and activated on the channel.
The deskew time. CT1, between the last valid signal of
address bus (and data bus on write sequences) and the
activation of address gate. measured at the device
interface, is 200 nanoseconds minimum. Upon
recognition of the address gate
by
the selected device,
the device activates the condition code in bus (and the
data bus on read sequences) and then activates address
gate return.
The condition code in bus (and data bus on read
sequences) must be activated prior to the address gate
return as seen at the device interface. These busses
must be held valid and must not change in value until
the deactivation of address gate and data strobe at the
device interface.
The permissible delay, T2, from address gate to
address gate return, as seen at the device interface is
3 microseconds maximum. Address gate return is timed
out
by
the channel. If address gate return does not
become active at the processor channel input vithin the
timeout period, condition code 0 (device not attached)
is returned to the I/O instruction and the sequence is
terminated as follows: address gate, address bus (and
data bus on write sequences) are deactivated. Data
strobe is not activated. Address gate is deactivated
prior to the deactivation of address bus as seen at the
device interface.
The permissible delay. T2, allows device
attachments further time to resolve conditions for
command acceptance or to initiate interlocked
activation with further outbound logic. However,
unless such functions are necessary, it is recommended
that address gate return be activated as soon as
possible for performance reasons.
GA34-0033
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