IBM Series 1 User Manual page 220

o
c
c
TNL: GN34-D368
to
GA34-0033-0 (February 4, 1977)
li~~i ~~guen£~§ Q~££i2tiQg
1 •
2.
The effect that Halt or
MeRK,
system reset, or power-on
reset must have, has been discussed at various points
throughout this chapter.
The Halt or MCHK and system reset tags, when occurring,
are active for 4.8 microseconds minimum as seen at the
device interface. Paver on reset sequencing is
discussed in the subsequent section, UElectrical
Characteristics".
3.
The deactivation of device interface signals active at
the time of the reset must be performed within 200
nanoseconds as seen at the device interface. The pre-
pare field and
IIIII
bit must be reset under the envelope
of a system reset.
4.
The processors may have unpredictable values on the
address, data,
and
status busses during resets.
Therefore, re~etting of registers must not depend on
the values
of
these busses.
5. For specific intormation concerning a reset sequence in
conjunction
with
another sequence, refer to
the
description of the basic sequences in earlier portions
at this section.
Processor I/O Channel 2-43