IBM Series 1 User Manual page 216

Hide thumbs Also See for Series 1:
Table of Contents

Advertisement

o
o
TNL: GN34-0368 to GA34-0033-0 (February 4,1977)
Refer
to Fiqure 2-14.
The processor initiated IPL sequence
is executed as follows:
1 •
The initiate IPL line is
activated
at
the
processor
channel
output, along with status bus bit
a
or 1, as a
result of pressing the load key.
status bus bit 0
and
1
reflect
the
position
of
the
IPL
source switch,
primary or alternate, at the
time
the
load
key
was
pressed.
The
first
system
reset in the sequence is
also activated
at this
time.
Initiate
IPL
and
the
status
bus
are held valid until the activation of the
1PL tag at the processor channel input after the
first
sytem reset is deactivated.
On
the activation of the logical
'AND' of
initiate
IPL
and system reset, the device must dc reset the
IPL
tag within 200
ns,
T1, as seen at the device interface.
On
activation
of
the
first system reset, the device
executes all other system reset functions.
Because
of
possible
skew,
system
reset may lag initiate IPL and
the status bus at the device interface.
Therefore, the
IPL
tag
may
temporarily
become active at the device
interface prior to
the
first
system
reset.
However,
the
processor
channel
ignores the IPL tag during the
initial part of the sequence and does
not
examine
it
until the first system reset has been
activated.
In no case should the device use the
leading-edge
transition
of the first system reset.
This is because
the first system reset could also lead the initiate 1PL
and status bus at the device interface.
2.
The
first
system
reset
is deactivated after a time,
CT1,
of
4.8
microseconds
minimum
at
the
device
interface.
The
IPL
source device then activates the
1PL tag.
The time, T2, from the
deactivation
of
the
first
system
reset
to
the activation of the 1PL tag
must be
g~eater
than
zero
as
seen
at
the
device
interface,
but
the
maximum time is device dependent.
This maximum time
should
be
kept
within
reasonable
limits, and generally this time should only depend upon
electronic rather than mechanical delays.
3.
As a result
of
1PL
going
active,
initiate
IPL
is
deactivated.
The
status
bus
is
not
valid for the
primary/alternate selection portion of the 1PL sequence
after the time when initiate IPL is deactivated.
Processor I/O Channel
2-37

Advertisement

Table of Contents
loading

Table of Contents