IBM Series 1 User Manual page 248

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TNL: GN34-0368 to GA34-0033-0 (February 4, 1977)
Figure 6-2 is a timing diagram for a typical output
sequence.
An
output sequence is executed as follows:
1. Function, modifier, device address bits, and data are
placed on their appropriate lines.
2. The
I/O
active tag is skewed (at least 200 nanoseconds)
and activated on the interface.
3. Upon recognition of address compare and I/O active, the
device raises the select response tag. Once raised,
this tag must be held active at least until the fall of
the I/O active tag. Condition code in must be active
until strobe becomes active or until I/O active becomes
inactive for the duration of the select response tag.
4.
Strobe is activated and dropped.*
*
If the DPC adapter feature is configured without
the parity option and a parity error is detected
between the processor I/O channel and the feature,
strobe is not activated except during the Device
Reset command.
S. The I/O
active tag is deactivated.
6. Upon recognition of the absence of the I/O active tag,
the device drops select response and condition code in.
7. The function, function modifier, device address, and
data busses are deactivated.
Figure 6-2. Output sequence timing diagram
Control lines
and data bus out
I/O active
Strobe (device)
Select response
Condi tion code in
Output sequence
Customer DPC Adapter 6-9