IBM Series 1 User Manual page 16

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INTRODUCTION
Input/output devices communicate with the processor and main
storage devices through the processor I/O channel.
Attachment of the devices to the channel is through an I/O
adapter or I/O attachment logic card.
The channel directs the flow of information between the
I/O devices, the processor, and main storage.
A
maximum of
256 devices can be addressed.
The processor I/O channel supports the following basic
types of operations:
• Direct program control
(DPC)
operations -- An immediate
data transfer is made between main storage and the
device for each Operate I/O instruction. The data may
consist of one byte or one word. The operation mayor
may not terminate with an interrupt.
•
Cycle steal operations An Operate I/O instruction
can initiate cycle stealing data transfers of up to
65,
535 bytes (per device control block) between main
storage and the device. Cycle steal operations are
overlapped with processing operations. Word or byte
transfers, command and data chaining, burst mode, and
program controlled interrupts can
be
supported.
• Interrupt servicing four preemptive priority
interrupt levels are available to facilitate device
service. The device interrupt level is assignable
by
the program. In addition, the device interrupt
capability can
be
masked under program control.
• Initial program load (LPL) operations A record
consisting of initial instructions for the processor is
read into storage from either a local I/O device or
from a host system.
The channel provides comprehensive error checking
including timeouts, sequence checking, and parity checking.
Reporting of errors, exceptions, and status is accomplished
by (1)
recording condition codes in the processor during
execution of Operate I/O instructions, and (2) recording
condition codes and an interrupt information byte (IIB) in
the processor during interrupt acceptance. Additional
sta tus words may be used .by the device as necessary to
describe its status.
The I/O Channel is asynchronous and multidropped.
Asynchronous means there are no timing restrictions inherent
in the architecture. The response from a given I/O device
triggers the next sequential action rather than a specified
Processor I/O Channel 2-1