IBM Series 1 User Manual page 36

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In subsequent sections, each major sequence is
described. Timing diagrams are used to show the important
timing relationships that the designer needs to adhere to
(or be aware of) when designing an I/O attachment for the
I/O channel.
~imings
on the diagram are divided into tvo
ma jor groups:
CT
T
channel times
attachment controlled times
The designer has no control over channel times, but he
must be aware of them. The designer does have control of
the T-tiaes. These are considered attachment dependent
times.
The diagrams use the convention of an up level to
denote a tag active or a bus value valid.
The following abbreviations are also used on the timing
diagraas:
LVS
LIS
last valid signal, occurring in time, of a group
of signals being activated on the channel. The
group is linked
by
short dotted lines on the
timing diagrams.
last invalid signal, occurring in time, of a group
of signals being deactivated on the channel. The
group is linked by short vertical dotted lines on
the timing diagrams.
( ; The designer should ensure that the signals he presents
c
to the I/O channel meet the specified T-times as shown on
the timing diagrams. Since the designer does not control
the loading at the output of the drivers in a given
configuration, these timings should
be
met assuming the
m.aximum loading permissible for the particular drivers being
used. There are cases where differences in driver delays
must be considered. For example, certain signals must be
deactivated prior to a tag being dropped at the device
adapter interface. In such cases one driver can be
considered
at
nominal delay, the other at worst case delay,
with both at maximum load.
Refer to Figure
2-8. DPe
write and DPe read sequences are
executed as follows:
1. Address bus bits 00--15 and address bus bit 16 (and the
data bus on write sequences) are activated by the
channel. These busses are held valid until the fall of
address gate return as seen at the processor channel
input.
Processor I/O Channel 2-21