IBM Series 1 User Manual page 38

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3.
Data strobe is activated. The time between address
gate return and data strobe activation, CT2, is
100
nanoseconds m1n1mum as seen at the device interface.
The duration of data strobe, CT3, as seen at the device
interface is 200 nanoseconds m1n1mum. If a parity
error is detected
by
the channel during a read
sequence, the data strobe is not activated.
4. Data strobe (if it has been activate~ and address gate
are deactivated simultaneously at the processor channel
output. As denoted by the relationship of CT3 and CT4
in Figure 2-8, data strobe may extend beyond the active
envelope of address gate by 100 nanoseconds maximum,
but the overlap of data strobe and address gate is
100
nanoseconds minimum as seen at the device interface.
5. Upon the deactivation of both address gate and data
strobe, the device deactivates the condition code in
bus (also data bus on read sequences), and address gate
return. The condition code in bus (and data bus on
read sequences) must be deactivated prior to the
deactivation of address gate return. The permissible
delay. TS. from the deactivation of both address gate
and data strobe to the deactivation of address gate
return is 3 microseconds maximum. This delay allows
the device attachments to generate additional strobes,
to do additional resetting, and to accomplish
interlocked deactivation with outbound logic. Unless
such functions are necessary however, it is recommended
that address gate be deactivated as soon as possible
for performance reasons. All device actions for the
command must take place before deactivating address
gate return.
6. The total duration of the DPC sequence is timed out
by
the channel for error detection purposes. The total
duration is measured as the time from activation of
address bus bit
16
to the deactivation of address gate
return. If address gate return is not deactivated
within the timeout, a machine check occurs, and the
channel activates the Halt or MCHK line. If the device
attachment adheres to the specified times over which it
has control, the total duration of the sequence viII be
within this channel timeout under normal operation.
Processor I/O Channel 2-23