IBM Series 1 User Manual page 249

TNL: GN34-0368 to GA34-0033-0 (February 4, 1977)
Figure 6-3 is a timing diagram for a typical input sequence.
An input sequence is executed as follows:
1. Function, modifier, and device address bits are placed
on
their appropriate lines.
2. The I/O active tag is skewed (at least 200 nanoseconds)
and
activated on the interface~
3. Upon recognition of address compare and I/O active, the
device raises the select response tag. Once raised,
this tag must be held active at least until the fall of
the I/O active tag. Data bus in and condition code in
must be active until strobe becomes active or until I/O
active becomes inactive for the duration of the select
response tag.
4. Strobe is activated and dropped. However, should a
parity error be detected
by
the processor this tag is
not acti va ted.
5. The I/O active tag is deactivated.
6. Upon recognition of the absence of the I/O active tag,
the device drops select response, condition code in,
and
data bus in.
Figure 6-3. Input sequence timing diagram
Input sequence
Control lines ")
I/O active
Strobe (device)
Select response
Condition code in
and data bus in
6-10
"20011::
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GA34-0033