IBM Series 1 User Manual page 28

c
c
Bits
0
and
1
of the status bus are also used for
selecting the primary and alternate 1PL source respectively.
The appropriate bit of the status bus is activated with the
ini tiate 1PL si.gnal to accomplish this selection. Only one
device can be configured as a primary 1PL source and only
one device can be configured as an alternate 1PL source at
one time.
~g st£2be. This is an outbound tag to the I/O device on:
OPC, interrupt, or cycle steal service sequences. This tag
can be used
by I/O
devices to:
(1)
accompl ish control
actions,
(2)
register data on outbound transfers, and
(3)
accoaplish appropriate data resets on inbound transfers.
Data strobe alvays occurs on normal DPC write, cycle steal,
and interrupt service sequences. On
ope
read sequences,
data strobe is not activated if the channel detects a parity
error.
Initiate IPL. This is an outbound tag from the channel to
the 1PL source
when
the
IPt
is initiated by the processor
Load key. The initiate IPL tag is singular in nature and
meaning. It is a signal to the IPL source that the
processor requires an IPL. The receiver for this tag is
always enabled.
Bits
0
and 1 of the status bus are used for selecting
the primary and alternate sources respectively; see "Status
Bus
tl •
1PL. This is an inbound tag
(1)
from the IPL source
activated
in response to the initiate IPL tag or (2) from a
host system to signal the processor that the host is
initiating an IPL action. The storage load itself takes
place via the cycle steal mechanism.
Halt 2£ MCH!. This is
an
outbound tag received by all I/O
devices. The tag means that either:
(1)
a Halt command
has been issued
by
the program or (2) a machine check class
interrupt (excluding a storage parity check) has occurred.
When the tag is detected by an I/O device, the device must
disable selection, block poll propagation, clear any status,
states, requests, interface control logic, and registers
with the following exceptions:
• Residual address
• Prepare level and I-bit
• Output sensor points
• Timer values
• Those registers not addressable by the software
The receiver for the halt or
MeRK
tag is always
enabled.
Processor I/O Channel 2-13