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Nations N32G43 Series Manuals
Manuals and User Guides for Nations N32G43 Series. We have
1
Nations N32G43 Series manual available for free PDF download: User Manual
Nations N32G43 Series User Manual (654 pages)
32-bit ARM Cortex-M4F microcontroller
Brand:
Nations
| Category:
Microcontrollers
| Size: 12 MB
Table of Contents
Table of Contents
2
Abbreviations in the Text
24
Describes the List of Abbreviations Used in the Register Table
24
Available Peripherals
24
Memory and Bus Architecture
25
System Architecture
25
Bus Architecture
25
Figure 2-1 Bus Architecture
25
Bus Address Mapping
26
Table 2-1 List of Peripheral Register Addresses
27
Figure 2-2 Bus Address Map
27
Boot Management
29
Table 2-2 List of Boot Mode
30
Memory System
31
FLASH Specification
31
Table 2-3 Flash Bus Address List
32
Table 2-4 Option Byte List
36
Table 2-5 Read Protection Configuration List
38
Table 2-6 Flash Read-Write-Erase (1) Permission Control Table
39
Icache
43
Sram
45
FLASH Registers
45
Table 2-7 FLASH Register Overview
45
Power Control (PWR)
55
General Description
55
Power Supply
55
Power Supply Supervisor
56
Figure 3-1 Power Supply Block Diagram
56
Figure 3-2 Brown-Out Reset (BOR) Waveform
57
Power Modes
58
Table 3-1 Power Modes
58
Figure 3-3 PVD Threshold Waveform
58
Table 3-2 Blocks Running State
59
RUN Mode
60
SLEEP Mode
61
LOW POWER RUN Mode
62
LOW POWER SLEEP Mode
63
STOP2 Mode
63
STANDBY Mode
64
Low-Power Auto-Wakeup (AWU) Mode
65
PWR Registers
66
PWR Register Overview
66
Power Control Register 1 (PWR_CTRL1)
66
Table 3-3 PWR Register Overview
66
Power Control Register 2 (PWR_CTRL2)
67
Power Control Register 3 (PWR_CTRL3)
68
Power Status Register 1 (PWR_STS1)
70
Power Status Register 1 (PWR_STS1)
71
Power Status Clear Register (PWR_STSCLR)
72
Reset and Clock Control (RCC)
73
Reset Control Unit
73
Power Reset
73
System Reset
73
Low Power Domain Reset
74
Figure 4-1 System Reset Generation
74
Clock Control Unit
75
Clock Tree Diagram
76
HSE Clock
76
Figure 4-2 Clock Tree
76
HSI Clock
77
Figure 4-3 HSE/LSE Clock Source
77
MSI Clock
78
PLL Clock
78
Figure 4-4 PLL Clock Source Selection
78
LSE Clock
79
LSI Clock
79
System Clock (SYSCLK) Selection
80
Clock Security System (CLKSS)
80
LSE Clock Security System (LSECSS)
80
RTC Clock
81
Watchdog Clock
81
Clock Output (MCO)
81
RCC Registers
81
RCC Register Overview
82
Table 4-1 RCC Register Overview
82
Clock Control Register (RCC_CTRL)
83
Clock Configuration Register (RCC_CFG)
85
Clock Interrupt Register (RCC_CLKINT)
88
APB2 Peripheral Reset Register (RCC_APB2PRST)
91
APB1 Peripheral Reset Register (RCC_APB1PRST)
93
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
95
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
96
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
98
LOW POWER Domain Control Register (RCC_LDCTRL)
100
Clock Control/Status Register (RCC_CTRLSTS)
102
AHB Peripheral Reset Register (RCC_AHBPRST)
104
Clock Configuration Register 2 (RCC_CFG2)
105
Clock Configuration Register 3 (RCC_CFG3)
107
Retention Domain Control Register (RCC_RDCTRL)
108
PLL and HSI Configuration Register (RCC_PLLHSIPRE)
109
SRAM Control/Status Register (RCC_SRAM_CTRLSTS)
110
GPIO and AFIO
111
Summary
111
I/O Function Description
112
I/O Mode Configuration
112
Table 5-1 I/O Port Configuration Table
112
Figure 5-1 Basic Structure of I/O Port
112
Table 5-2 Input and Output Characteristics of Different Configurations
113
Figure 5-2 Input Floating/Pull-Up/Pull-Down Configuration
114
Figure 5-3 Output Mode Configuration
115
Figure 5-4 Alternate Function Configuration
116
Status after Reset
117
Individual Bit Setting and Bit Clearing
117
Figure 5-5 High Impedance Analog Mode Configuration
117
External Interrupt/Wake-Up Line
118
Alternate Function
118
Table 5-3 Debug Port Image
119
Table 5-4 ADC External Trigger Injection Conversion Alternate Function Remapping
119
Table 5-5 ADC External Trigger Regular Conversion Alternate Function Remapping
120
Table 5-6 TIM1 Alternate Function Remapping
120
Table 5-7 TIM2 Alternate Function Remapping
120
Table 5-8 TIM3 Alternate Function Remapping
121
Table 5-9 TIM4 Alternate Function Remapping
121
Table 5-10 TIM5 Alternate Function Remapping
121
Table 5-11 TIM8 Alternate Function Remapping
121
Table 5-12 TIM9 Alternate Function Remapping
122
Table 5-13 LPTIM Alternate Function Remapping
122
Table 5-14 CAN Alternate Function Remapping
122
Table 5-15 USART1 Alternate Function Remapping
123
Table 5-16 USART2 Alternate Function Remapping
123
Table 5-17 USART3 Alternate Function Remapping
123
Table 5-18 UART4 Alternate Function Remapping
124
Table 5-19 UART5 Alternate Function Remapping
124
Table 5-20 LPUART Alternate Function Remapping
124
Table 5-21 I2C1 Alternate Function Remapping
125
Table 5-22 I2C2 Alternate Function Remapping
126
Table 5-23 SPI1 Alternate Function Remapping
126
Table 5-24 SPI2/I2S2 Alternate Function Remapping
127
Table 5-25 COMP1 Alternate Function Remapping
127
Table 5-26 COMP2 Alternate Function Remapping
127
IO Configuration of Peripherals
128
Table 5-27 EVENTOUT Alternate Function Remapping
128
Table 5-28 RTC Alternate Function Remapping
128
Table 5-29 ADC/DAC
128
Table 5-30 TIM1/TIM8
128
Table 5-31 TIM2/3/4/5/9
128
Table 5-32 LPTIM
128
Table 5-33 CAN
129
Table 5-34 USART
129
Table 5-35 UART
129
Table 5-36 LPUART
129
Table 5-37 I2C
129
Table 5-38 SPI-I2S
129
GPIO Locking Mechanism
130
Table 5-39 USB
130
Table 5-40 JTAG/SWD
130
Table 5-41 Other
130
GPIO Registers
131
GPIO Registers Overview
131
Table 5-42 GPIO Registers Overview
131
GPIO Mode Description Register (Gpiox_Pmode)
132
GPIO Type Definition (Gpiox_Potype)
133
GPIO Port Slew Rate Configuration Register (Gpiox_Sr)
133
GPIO Pull-Up/Pull-Down Description Register (Gpiox_Pupd)
134
GPIO Input Data Register (Gpiox_Pid)
134
GPIO Output Data Register (Gpiox_Pod)
135
GPIO Bit Set/Clear Register (Gpiox_Pbsc)
135
GPIO Configuration Lock Register (Gpiox_Plock)
136
GPIO Alternate Function Low Register (Gpiox_Afl)
137
GPIO Alternate Function High Register (Gpiox_Afh)
137
GPIO Bit Clear Register (Gpiox_Pbc)
138
GPIO Driver Strength Configuration Register (Gpiox_Ds)
138
AFIO Registers
139
AFIO Register Overview
139
Table 5-43 AFIO Register Overview
139
AFIO Mapping Configuration Control Register (AFIO_RMP_CFG)
140
AFIO External Interrupt Configuration Register 1(AFIO_EXTI_CFG1)
141
AFIO External Interrupt Configuration Register 2(AFIO_EXTI_CFG2)
141
AFIO External Interrupt Configuration Register 3(AFIO_EXTI_CFG3)
142
AFIO External Interrupt Configuration Register 4(AFIO_EXTI_CFG4)
143
Interrupts and Events
145
Nested Vector Interrupt Register
145
Systick Calibration Value Register
145
Interrupt and Exception Vectors
145
Table 6-1 Vector Table
145
External Interrupt/Event Controller (EXTI)
148
Introduction
148
Main Features
148
Functional Description
149
Figure 6-1 External Interrupt/Event Controller Block Diagram
149
EXTI Line Mapping
151
Figure 6-2 External Interrupt Generic I/O Mapping
151
EXTI Registers
152
EXTI Register Overview
152
EXTI Interrupt Mask Register (EXTI_IMASK)
152
Table 6-2 EXTI Register Overview
152
EXTI Event Mask Register (EXTI_EMASK)
153
EXTI Rising Edge Trigger Configuration Register (EXTI_RT_CFG)
153
EXTI Falling Edge Trigger Configuration Register (EXTI_FT_CFG)
154
EXTI Software Interrupt Event Register (EXTI_SWIE)
154
EXTI Pending Register (EXTI_PEND)
154
EXTI Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
155
DMA Controller
156
Introduction
156
Main Features
156
Block Diagram
157
Function Description
157
DMA Operation
157
Figure 7-1 DMA Block Diagram
157
Channel Priority and Arbitration
158
DMA Channels and Number of Transfers
158
Programmable Data Bit Width, Alignment and Endians
158
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
159
Peripheral/Memory Address Incrementation
160
Channel Configuration Procedure
160
Flow Control
161
Table 7-2 Flow Control Table
161
Circular Mode
162
Error Management
162
Interrupt
162
Table 7-3 DMA Interrupt Request
162
DMA Request Mapping
163
Table 7-4 DMA Request Mapping
163
DMA Registers
164
DMA Register Overview
164
Table 7-5 DMA Register Overview
164
DMA Interrupt Status Register (DMA_INTSTS)
166
DMA Interrupt Flag Clear Register (DMA_INTCLR)
167
DMA Channel X Configuration Register (Dma_Chcfgx)
167
DMA Channel X Transfer Number Register (Dma_Txnumx)
169
DMA Channel X Peripheral Address Register (Dma_Paddrx)
170
DMA Channel X Memory Address Register (Dma_Maddrx)
170
DMA Channel X Channel Request Select Register (Dma_Chselx)
171
CRC Calculation Unit
174
CRC Introduction
174
CRC Main Features
174
CRC32 Module
174
CRC16 Module
174
CRC Function Description
175
Crc32
175
Crc16
175
Figure 8-1 CRC Calculation Unit Block Diagram
175
CRC Registers
176
CRC Register Overview
176
CRC32 Data Register (CRC_CRC32DAT)
176
CRC32 Independent Data Register (CRC_CRC32IDAT)
176
Table 8-1 CRC Register Overview
176
CRC32 Control Register (CRC_CRC32CTRL)
177
CRC16 Control Register (CRC_CRC16CTRL)
177
CRC16 Input Data Register (CRC_CRC16DAT)
178
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
178
LRC Result Register (CRC_LRC)
179
Cryptographic Algorithm Hardware Acceleration Engine (SAC)
180
Advanced-Control Timers (TIM1 and TIM8)
181
TIM1 and TIM8 Introduction
181
Main Features of TIM1 and TIM8
181
TIM1 and TIM8 Function Description
182
Time-Base Unit
182
Figure 10-1 Block Diagram of TIM1 and TIM8
182
Counter Mode
183
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
183
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
185
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
186
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
188
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
189
Repetition Counter
190
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
190
Figure 10-8 Repeat Count Sequence Diagram in Down-Counting Mode
191
Figure 10-9 Repeat Count Sequence Diagram in Up-Counting Mode
192
Figure 10-10 Repeat Count Sequence Diagram in Center-Aligned Mode
192
Clock Selection
193
Figure 10-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
193
Figure 10-12 TI2 External Clock Connection Example
194
Figure 10-13 Control Circuit in External Clock Mode 1
195
Figure 10-14 External Trigger Input Block Diagram
195
Capture/Compare Channels
196
Figure 10-15 Control Circuit in External Clock Mode 2
196
Figure 10-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
197
Figure 10-17 Capture/Compare Channel 1 Main Circuit
198
Input Capture Mode
199
Figure 10-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
199
Figure 10-19 Output Part of Channelx (X= 4)
199
PWM Input Mode
200
Forced Output Mode
201
Figure 10-20 PWM Input Mode Timing
201
Output Compare Mode
202
PWM Mode
203
Figure 10-21 Output Compare Mode, Toggle on OC1
203
Figure 10-22 Center-Aligned PWM Waveform (AR=8)
204
Figure 10-23 Edge-Aligned PWM Waveform (APR=8)
205
One-Pulse Mode
206
Clearing the Ocxref Signal on an External Event
207
Complementary Outputs with Dead-Time Insertion
208
Figure 10-24 Clearing the Ocxref of Timx
208
Figure 10-25 Complementary Output with Dead-Time Insertion
209
Break Function
210
Debug Mode
212
Timx and External Trigger Synchronization
212
Figure 10-26 Output Behavior in Response to a Break
212
Figure 10-27 Control Circuit in Reset Mode
213
Figure 10-28 Control Circuit in Trigger Mode
214
Figure 10-29 Control Circuit in Gated Mode
215
Timer Synchronization
216
6-Step PWM Generation
216
Figure 10-30 Control Circuit in Trigger Mode + External Clock Mode2
216
Encoder Interface Mode
217
Figure 10-31 6-Step PWM Generation, COM Example (OSSR=1)
217
Table 10-1 Counting Direction Versus Encoder Signals
218
Figure 10-32 Example of Counter Operation in Encoder Interface Mode
218
Interfacing with Hall Sensor
219
Figure 10-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
219
Figure 10-34 Example of Hall Sensor Interface
220
Timx Registers(X=1, 8)
221
Timx Register Overview
221
Table 10-2 Timx Register Overview
221
Control Register 1 (Timx_Ctrl1)
222
Control Register 2 (Timx_Ctrl2)
224
Slave Mode Control Register (Timx_Smctrl)
226
Table 10-3 Timx Internal Trigger Connection
228
Dma/Interrupt Enable Registers (Timx_Dinten)
229
Status Registers (Timx_Sts)
230
Event Generation Registers (Timx_Evtgen)
232
Capture/Compare Mode Register 1 (Timx_Ccmod1)
233
Capture/Compare Mode Register 2 (Timx_Ccmod2)
236
Capture/Compare Enable Registers (Timx_Ccen)
238
Table 10-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
240
Counters (Timx_Cnt)
241
Prescaler (Timx_Psc)
241
Auto-Reload Register (Timx_Ar)
241
Repeat Count Registers (Timx_Repcnt)
242
Capture/Compare Register 1 (Timx_Ccdat1)
242
Capture/Compare Register 2 (Timx_Ccdat2)
243
Capture/Compare Register 3 (Timx_Ccdat3)
243
Capture/Compare Register 4 (Timx_Ccdat4)
244
Break and Dead-Time Registers (Timx_Bkdt)
244
DMA Control Register (Timx_Dctrl)
246
DMA Transfer Buffer Register (Timx_Daddr)
247
Capture/Compare Mode Registers 3(Timx_Ccmod3)
248
Capture/Compare Register 5 (Timx_Ccdat5)
248
Capture/Compare Register 6 (Timx_Ccdat6)
249
General-Purpose Timers (TIM2, TIM3, TIM4, TIM5 and TIM9)
250
General-Purpose Timers Introduction
250
Main Features of General-Purpose Timers
250
General-Purpose Timers Description
251
Time-Base Unit
251
Figure 11-1 Block Diagram of Timx(X=2, 3 ,4 ,5 and 9
251
Counter Mode
252
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
252
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
254
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
255
Figure 11-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
256
Figure 11-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
257
Clock Selection
258
Figure 11-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
258
Figure 11-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
259
Figure 11-9 TI2 External Clock Connection Example
260
Figure 11-10 Control Circuit in External Clock Mode 1
261
Figure 11-11 External Trigger Input Block Diagram
261
Capture/Compare Channels
262
Figure 11-12 Control Circuit in External Clock Mode 2
262
Figure 11-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
263
Figure 11-14 Capture/Compare Channel 1 Main Circuit
264
Input Capture Mode
265
Figure 11-15 Output Part of Channelx (X = 1,2,3,4;Take Channel 4 as an Example
265
PWM Input Mode
266
Forced Output Mode
267
Output Compare Mode
267
Figure 11-16 PWM Input Mode Timing
267
PWM Mode
269
Figure 11-17 Output Compare Mode, Toggle on OC1
269
Figure 11-18 Center-Aligned PWM Waveform (AR=8)
270
Figure 11-19 Edge-Aligned PWM Waveform (APR=8)
271
One-Pulse Mode
272
Figure 11-20 Example of One-Pulse Mode
272
Clearing the Ocxref Signal on an External Event
273
Debug Mode
274
Timx and External Trigger Synchronization
274
Timer Synchronization
274
Figure 11-21 Control Circuit in Reset Mode
274
Figure 11-22 Block Diagram of Timer Interconnection
275
Figure 11-23 TIM2 Gated by OC1REF of TIM1
276
Figure 11-24 TIM2 Gated by Enable Signal of TIM1
277
Figure 11-25 Trigger TIM2 with an Update of TIM1
278
Encoder Interface Mode
279
Figure 11-26 Triggers Timers 1 and 2 Using the TI1 Input of TIM1
279
Table 11-1 Counting Direction Versus Encoder Signals
280
Figure 11-27 Example of Counter Operation in Encoder Interface Mode
280
Interfacing with Hall Sensor
281
Timx Registers(X=2, 3 ,4 ,5 and 9)
281
Timx Register Overview
281
Figure 11-28 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
281
Control Register 1 (Timx_Ctrl1)
283
Control Register 2 (Timx_Ctrl2)
285
Slave Mode Control Register (Timx_Smctrl)
286
Dma/Interrupt Enable Registers (Timx_Dinten)
288
Table 11-3 Timx Internal Trigger Connection
288
Status Registers (Timx_Sts)
290
Event Generation Registers (Timx_Evtgen)
291
Capture/Compare Mode Register 1 (Timx_Ccmod1)
292
Capture/Compare Mode Register 2 (Timx_Ccmod2)
295
Capture/Compare Enable Registers (Timx_Ccen)
297
Counters (Timx_Cnt)
298
Table 11-4 Output Control Bits of Standard Ocx Channel
298
Prescaler (Timx_Psc)
299
Auto-Reload Register (Timx_Ar)
299
Capture/Compare Register 1 (Timx_Ccdat1)
299
Capture/Compare Register 2 (Timx_Ccdat2)
300
Capture/Compare Register 3 (Timx_Ccdat3)
300
Capture/Compare Register 4 (Timx_Ccdat4)
301
DMA Control Register (Timx_Dctrl)
301
DMA Transfer Buffer Register (Timx_Daddr)
302
Basic Timers (TIM6 and TIM7)
304
Basic Timers Introduction
304
Main Features of Basic Timers
304
Figure 12-1 Block Diagram of Timx(X = 6 and 7
304
Basic Timers Description
305
Time-Base Unit
305
Figure 12-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
305
Counter Mode
306
Figure 12-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
307
Figure 12-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
308
Clock Selection
309
Debug Mode
309
Timx Registers(X = 6 and 7)
309
Figure 12-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
309
Timx Register Overview
310
Control Register 1 (Timx_Ctrl1)
310
Table 12-1 Timx Register Overview
310
Control Register 2 (Timx_Ctrl2)
311
Dma/Interrupt Enable Registers (Timx_Dinten)
312
Status Registers (Timx_Sts)
312
Event Generation Registers (Timx_Evtgen)
313
Counters (Timx_Cnt)
313
Prescaler (Timx_Psc)
313
Automatic Reload Register (Timx_Ar)
314
Low Power Timer (LPTIM)
315
Introduction
315
Main Features
315
Block Diagram
316
Function Description
316
LPTIM Clocks and On-Off Control
316
Figure 13-1 LPTIM Diagram
316
Prescaler
317
Glitch Filter
317
Table 13-1 Pre-Scaler Division Ratios
317
Timer Enable
318
Trigger Multiplexer
318
Table 13-2 9 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits
318
Figure 13-2 Glitch Filter Timing Diagram
318
Operating Mode
319
Figure 13-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
319
Figure 13-4 PTIM Output Waveform, Single Counting Mode Configuration
320
Waveform Generation
321
Figure 13-5 LPTIM Output Waveform, Single Counting Mode Configuration and One-Time Mode Activated
321
Register Update
322
Figure 13-6 Waveform Generation
322
Counter Mode
323
Encoder Mode
324
Table 13-3 Encoder Counting Scenarios
324
Non-Orthogonal Encoder Mode
325
Figure 13-7 Encoder Mode Counting Sequence
325
Timeout Function
326
Figure 13-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally
326
Figure 13-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working
326
LPTIM Interrupts
327
LPTIM Registers
327
LPTIM Register Overview
327
Table 13-4 Interruption Events
327
LPTIM Interrupt and Status Register (LPTIM_INTSTS)
328
LPTIM Interrupt Clear Register (LPTIM_INTCLR)
329
LPTIM Interrupt Enable Register (LPTIM_INTEN)
330
LPTIM Configuration Register (LPTIM_CFG)
331
LPTIM Control Register (LPTIM_CTRL)
334
LPTIM Compare Register (LPTIM_COMP)
334
LPTIM Auto-Reload Register (LPTIM_ARR)
335
LPTIM Counter Register (LPTIM_CNT)
335
Real Time Clock (RTC)
337
Introduction
337
Main Feature
337
Function Description
339
RTC Block Diagram
339
Figure 14-1 RTC Block Diagram
339
GPIO Controlled by RTC
340
RTC Register Write Protection
340
RTC Clock and Prescaler
340
RTC Calendar
341
Calendar Initialization and Configuration
341
Calendar Reading
342
Calibration Clock Output
343
Programmable Alarm
343
Alarm Configuration
343
Alarm Output
343
Periodic Automatic Wakeup
344
Wakeup Timer Configuration
344
Timestamp Function
344
Tamper Detection
345
Daylight Saving Time Configuration
346
RTC Reset
346
RTC Sub-Second Register Shift Operation
346
RTC Digital Clock Precision Calibration
346
RTC Low Power Mode
348
RTC Registers
348
RTC Register Overview
348
Table 14-1 RTC Register Overview
348
RTC Calendar Time Register (RTC_TSH)
349
RTC Calendar Date Register (RTC_DATE)
350
RTC Control Register (RTC_CTRL)
351
RTC Initial Status Register (RTC_INITSTS)
353
RTC Prescaler Register (RTC_PRE)
355
RTC Wakeup Timer Register (RTC_WKUPT)
356
RTC Alarm a Register (RTC_ALARMA)
356
RTC Alarm B Register (RTC_ ALARMB)
357
RTC Write Protection Register (RTC_WRP)
358
RTC Sub-Second Register (RTC_SUBS)
359
RTC Shift Control Register (RTC_ SCTRL)
359
RTC Timestamp Time Register (RTC_TST)
360
RTC Timestamp Date Register (RTC_TSD)
360
RTC Timestamp Sub-Second Register (RTC_TSSS)
361
RTC Calibration Register (RTC_CALIB)
362
RTC Tamper Configuration Register(Rtc_ TMPCFG
362
RTC Alarm a Sub-Second Register (RTC_ ALRMASS)
365
RTC Alarm B Sub-Second Register (RTC_ ALRMBSS)
366
RTC Option Register (RTC_ OPT)
367
RTC Backup Registers (RTC_ BKP(1~20))
367
Independent Watchdog (IWDG)
368
Introduction
368
Main Features
368
Function Description
369
Register Access Protection
369
Figure 15-1 Functional Block Diagram of the Independent Watchdog Module
369
Debugging Mode
370
User Interface
370
Operate Flow
370
Table 15-1 IWDG Counting Maximum and Minimum Reset Time
370
IWDG Configuration Flow
371
IWDG Registers
371
IWDG Register Overview
371
Table 15-2 IWDG Registers Overview
371
IWDG Key Register (IWDG_KEY)
372
IWDG Pre-Scaler Register (IWDG_PREDIV)
372
IWDG Reload Register (IWDG_RELV)
373
IWDG Status Register (IWDG_STS)
373
Window Watchdog (WWDG)
375
Introduction
375
Main Features
375
Function Description
375
Figure 16-1 Watchdog Block Diagram
375
Timing for Refresh Watchdog and Interrupt Generation
376
Figure 16-2 Refresh Window and Interrupt Timing of WWDG
376
Debug Mode
377
User Interface
377
WWDG Configuration Flow
377
Table 16-1 Maximum and Minimum Counting Time of WWDG
377
WWDG Registers
378
WWDG Register Overview
378
WWDG Control Register (WWDG_CTRL)
378
WWDG Config Register (WWDG_CFG)
378
Table 16-2 WWDG Register Overview
378
WWDG Status Register (WWDG_STS)
379
Analog to Digital Conversion (ADC)
380
Introduction
380
Main Features
380
Function Description
381
ADC Clock
382
Table 17-1 ADC Pins
382
Figure 17-1 Block Diagram of a Single ADC
382
ADC Switch Control
383
Figure 17-2 ADC Clock
383
Channel Selection
384
Figure 17-3 ADC Channels and Pin Connections
385
Internal Channel
386
Single Conversion Mode
386
Continuous Conversion Mode
386
Timing Diagram
386
Analog Watchdog
387
Table 17-2 Analog Watchdog Channel Selection
387
Figure 17-4 Timing Diagram
387
Scanning Mode
388
Injection Channel Management
388
Discontinuous Mode
389
Figure 17-5 Injection Conversion Delay
389
Calibration
390
Data Aligned
390
Figure 17-6 Calibration Sequence Diagram
390
Programmable Channel Sampling Time
391
Externally Triggered Conversion
391
Table 17-3 Right-Align Data
391
Table 17-4 Left-Aligne Data
391
DMA Requests
392
Temperature Sensor
392
Table 17-5 ADC Is Used for External Triggering of Regular Channels
392
Table 17-6 ADC Is Used for External Triggering of Injection Channels
392
Temperature Sensor Using Flow
393
Figure 17-7 Temperature Sensor and VREFINT Diagram of the Channel
393
ADC Interrupt
394
ADC Registers
394
ADC Register Overview
394
Table 17-7 ADC Interrupt
394
Table 17-8 ADC Register Overview
394
ADC Status Register (ADC_STS)
395
ADC Control Register 1 (ADC_CTRL1)
397
ADC Control Register 2 (ADC_CTRL2)
399
ADC Sampling Time Register 1 (ADC_SAMPT1)
401
ADC Sampling Time Register 2 (ADC_ SAMPT2)
401
ADC Injected Channel Data Offset Register X (Adc_Joffsetx)(X=1
402
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
402
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
403
ADC Regular Sequence Register 1 (ADC_RSEQ1)
403
ADC Regular Sequence Register 2 (ADC_RSEQ2)
404
ADC Regular Sequence Register 3 (ADC_RSEQ3)
404
ADC Injection Sequence Register (ADC_JSEQ)
405
ADC Injection Data Register X (Adc_Jdatx) (X= 1
405
ADC Regulars Data Register (ADC_DAT)
406
ADC Differential Mode Selection Register (ADC_DIFSEL)
406
ADC Calibration Factor (ADC_CALFACT)
407
ADC Control Register 3 (ADC_CTRL3)
407
ADC Sampling Time Register 3 (ADC_SAMPT3)
409
Digital to Analog Conversion (DAC)
409
Introduction
409
Main Features
410
Table 18-1 DAC Pins
411
Figure 18-1 Block Diagram of a DAC Channel
411
DAC Function Description and Operation Description
412
DAC Enable
412
DAC Output Buffer
412
DAC Data Format
412
Figure 18-2 Data Register of Single DAC Channel Mode
412
DAC Trigger
413
DAC Conversion
413
Table 18-2 DAC External Trigger
413
DAC Output Voltage
414
DMA Requests
414
The Noise
414
Figure 18-3 Tine Diagram of Transitions with Trigger Disable
414
Triangular Wave Generation
415
Figure 18-4 LFSR Algorithm for DAC
415
Figure 18-5 DAC Conversion with LFSR Waveform Generation (Enable Software Trigger)
415
Figure 18-6 Triangle Wave Generation of DAC
416
Figure 18-7 DAC Conversion with Trigonometry Generation (Enable Software Trigger)
416
DAC Register
417
DAC Registers Overview
417
DAC Control Register (DAC_CTRL)
417
Table 18-3 DAC Registers Overview
417
DAC Software Trigger Register (DAC_SOTTR)
419
Bit Right Aligned Data Hold Register for DAC (DAC_DR12CH)
419
Bit Left Aligned Data Hold Register for DAC (DAC_DL12CH)
419
8-Bit Right-Aligned Data Hold Register for DAC (DAC_DR8CH)
420
DAC Data Output Register (DAC_DATO)
420
Comparator (COMP)
422
COMP System Connection Block Diagram
422
Figure 19-1 Comparator Controller Functional Diagram
422
COMP Features
423
COMP Configuration Process
423
COMP Working Mode
424
Window Mode
424
Independent Comparator
424
Comparator Interconnection
424
Interrupt
425
COMP Register
426
COMP Register Overview
426
Table 19-1 COMP Register Overview
426
COMP Interrupt Enable Register (COMP_INTEN)
427
COMP Low Power Select Register (COMP_LPCKSEL)
427
COMP Window Mode Register (COMP_WINMODE)
428
COMP Lock Register (COMP_LOCK)
428
COMP Control Register (COMP1_CTRL)
429
COMP Filter Register (COMP1_FILC)
431
COMP Filter Frequency Division Register (COMP1_FILP)
431
COMP Control Register (COMP2_CTRL)
432
COMP Filter Register (COMP2_FILC)
433
COMP Filter Frequency Division Register (COMP2_FILP)
434
COMP Output Select Register (COMP2_OSEL)
434
COMP Reference Voltage Register (COMP_VREFSCL)
435
COMP Test Register(COMP_TEST)
435
COMP Interrupt Status Register (COMP_INTSTS)
436
Operational Amplifier (OPAMP)
437
Main Features
437
OPAMP Function Description
437
OPAMP Working Mode
438
OPAMP Independent Op Amp Mode
438
Figure 20-1 Block Diagram of OPAMP1 and OPAMP2 Connection Diagram
438
OPAMP Follow Mode
439
Figure 20-2 Independent Op Amp Mode of OPAMP
439
OPAMP Internal Gain (PGA) Mode
440
Figure 20-3 Follow Mode
440
OPAMP with Filtered Internal Gain Mode
441
Figure 20-4 Internal Gain Mode
441
Figure 20-5 Internal Gain Mode with Filter
441
OPAMP Calibration
442
OPAMP Independent Write Protection
442
OPAMP TIMER Controls the Switching Mode
442
OPAMP Register
442
OPAMP Register Overview
442
Table 20-1 OPAMP Register Overview
442
OPAMP Control Status Register (OPAMP1_CS)
443
OPAMP Control Status Register (OPAMP2_CS)
444
OPAMP Lock Register (OPAMP_LOCK)
446
I 2 C Interface
447
Introduction
447
Main Features
447
Function Description
447
SDA and SCL Line Control
448
Software Communication Process
448
Figure 21-1 I 2 C Functional Block Diagram
449
Figure 21-2 I2C Bus Protocol
449
Figure 21-3 Slave Transmitter Transfer Sequence Diagram
452
Figure 21-4 Slave Receiver Transfer Sequence Diagram
453
Figure 21-5 Master Transmitter Transfer Sequence Diagram
455
Figure 21-6 Master Receiver Transfer Sequence Diagram
457
Error Conditions Description
458
DMA Application
459
Packet Error Check
460
Smbus
461
Table 21-1 Comparison between Smbus and I2C
461
Debug Mode
463
Interrupt Request
463
Table 21-2 I 2 C Interrupt Request
463
I2C Registers
464
I2C Register Overview
464
Table 21-3 I2C Register Overview
464
I2C Control Register 1 (I2C_CTRL1)
465
I2C Control Register 2 (I2C_CTRL2)
467
I2C Own Address Register 1 (I2C_OADDR1)
468
I2C Own Address Register 2 (I2C_OADDR2)
469
I2C Data Register (I2C_DAT)
469
I2C Status Register 1 (I2C_STS1)
470
I2C Status Register 2 (I2C_STS2)
473
I2C Clock Control Register (I2C_CLKCTRL)
474
I2C Rise Time Register (I2C_TMRISE)
475
Universal Synchronous Asynchronous Receiver Transmitter (USART)
477
Introduction
477
Main Features
477
Functional Block Diagram
478
Function Description
478
Figure 22-1 USART Block Diagram
478
USART Frame Format
479
Figure 22-2 Word Length = 8 Setting
479
Transmitter
480
Table 22-1 Stop Bit Configuration
480
Figure 22-3 Word Length = 9 Setting
480
Figure 22-4 Configuration Stop Bit
481
Receiver
482
Figure 22-5 TXC/TXDE Changes During Transmission
482
Figure 22-6 Start Bit Detection
483
Generation of Fractional Baud Rate
485
Table 22-2 Data Sampling for Noise Detection
485
Table 22-3 Error Calculation When Setting Baud Rate
486
Receiver's Tolerance Clock Deviation
487
Parity Control
487
Table 22-4 When Div_Decimal = 0. Tolerance of USART Receiver
487
Table 22-5 When Div_Decimal != 0. Tolerance of USART Receiver
487
Table 22-6 Frame Format
487
DMA Application
488
Figure 22-7 Transmission Using DMA
489
Hardware Flow Control
490
Figure 22-8 Reception Using DMA
490
Figure 22-9 Hardware Flow Control between Two USART
490
Figure 22-10 RTS Flow Control
491
Multiprocessor Communication
492
Figure 22-11 CTS Flow Controls
492
Figure 22-12 Mute Mode Using Idle Line Detection
493
Synchronous Mode
494
Figure 22-13 Mute Mode Detected Using Address Mark
494
Figure 22-14 USART Synchronous Transmission Example
495
Figure 22-15 USART Data Clock Timing Example (WL=0)
495
Single-Wire Half-Duplex Mode
496
Figure 22-16 USART Data Clock Timing Example (WL=1)
496
Figure 22-17 RX Data Sampling / Holding Time
496
Irda SIR ENDEC Mode
497
LIN Mode
498
Figure 22-18 Irdasirendec-Block Diagram
498
Figure 22-19 Irda Data Modulation (3/16)-Normal Mode
498
Figure 22-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
500
Smartcard Mode (ISO7816)
501
Figure 22-21 Break Detection and Framing Error Detection in LIN Mode
501
Figure 22-22 ISO7816-3 Asynchronous Protocol
502
Interrupt Request
503
Table 22-7 USART Interrupt Request
503
Figure 22-23 Use 1.5 Stop Bits to Detect Parity Errors
503
Mode Support
504
USART Registers
504
USART Register Overview
504
Table 22-8 USART Mode Setting
504
Table 22-9 USART Register Overview
504
USART Status Register (USART_STS)
505
USART Data Register (USART_DAT)
507
USART Baud Rate Register (USART_BRCF)
508
USART Control Register 1 Register (USART_CTRL1)
508
USART Control Register 2 Register (USART_CTRL2)
510
USART Control Register 3 Register (USART_CTRL3)
511
USART Guard Time and Prescaler Register (USART_GTP)
513
Low Power Universal Asynchronous Receiver Transmitter (LPUART)
515
Introduction
515
Main Features
515
Functional Block Diagram
516
Function Description
516
Figure 23-1 LPUART Block Diagram
516
LPUART Frame Format
517
Transmitter
517
Figure 23-2 Frame Format
517
Receiver
519
Figure 23-3 TXC Changes During Transmission
519
Fractional Baud Rate Generation
521
Table 23-1 Data Sampling for Noise Detection
521
Figure 23-4 Data Sampling for Noise Detection
521
Parity Control
522
DMA Application
523
Table 23-2 Parity Frame Format
523
Figure 23-5 Sending Using DMA
524
Hardware Flow Control
525
Figure 23-6 Receiving with DMA
525
Figure 23-7 Hardware Flow Control between Two LPUART
525
Figure 23-8 RTS Flow Control
526
Low Power Wake up
527
Interrupt Request
527
Table 23-3 LPUART Interrupt Requests
527
Figure 23-9 CTS Flow Control
527
LPUART Registers
528
LPUART Register Overview
528
LPUART Status Register (LPUART_STS)
528
Table 23-4 LPUART Register Overview
528
LPUART Interrupt Enable Register (LPUART_INTEN)
529
LPUART Control Register (LPUART_CTRL)
530
LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1)
531
LPUART Data Register (LPUART_DAT)
532
LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2)
532
LPUART Wake up Data Register (LPUART_WUDAT)
533
Serial Peripheral Interface/Inter-IC Sound (SPI/I 2 S)
534
Introduction
534
Main Features
534
SPI Features
534
I 2 S Features
534
SPI Function Description
535
General Description
535
Figure 24-1 SPI Block Diagram
535
Figure 24-2 Selective Management of Hardware/Software
536
Figure 24-3 Master and Slave Applications
537
SPI Work Mode
538
Figure 24-4 Data Clock Timing Diagram
538
Figure 24-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full
539
Duplex Mode
539
Figure 24-6 Schematic Diagram of TE/BUSY Change When Host Transmits Continuously in One-Way Only Mode
540
Figure 24-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode (BIDIRMODE=0 and RONLY=1)
541
Figure 24-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in Full
541
Duplex Mode
541
Figure 24-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit
542
Only Mode
542
Status Flag
544
Figure 24-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted
544
Discontinuously
544
Disabling the SPI
545
SPI Communication Using DMA
546
CRC Calculation
547
Figure 24-11 Transmission Using DMA
547
Figure 24-12 Reception Using DMA
547
Error Flag
548
SPI Interrupt
549
Table 24-1 SPI Interrupt Request
549
I 2 S Function Description
550
Figure 24-13 I 2 S Block Diagram
550
Supported Audio Protocols
551
Figure 24-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
552
Figure 24-15 I S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
552
Figure 24-16 I 2 S Philips Protocol Standard Waveform (16-Bit Extended to 32-Bit Packet Frame, CLKPOL = 0)
553
Figure 24-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
554
Figure 24-18 MSB Aligns 24-Bit Data, CLKPOL = 0
554
Figure 24-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
555
Figure 24-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
555
Figure 24-21 LSB Aligns 24-Bit Data, CLKPOL = 0
556
Figure 24-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
556
Figure 24-23 PCM Standard Waveform (16 Bits)
557
Figure 24-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
557
Clock Generator
558
Figure 24-25 I 2 S Clock Generator Structure
558
Figure 24-26 Audio Sampling Frequency Definition
558
I 2 S Transmission and Reception Sequence
559
Status Flag
561
Error Flag
562
I 2 S Interrupt
562
DMA Function
563
SPI and I S Registers
563
SPI Register Overview
563
Table 24-2 I 2 S Interrupt Request
563
Table 24-3 SPI Register Overview
563
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
564
SPI Control Register 2 (SPI_CTRL2)
566
SPI Status Register (SPI_STS)
567
SPI Data Register (SPI_DAT)
568
SPI CRC Polynomial Register (SPI_CRCPOLY) (Not Used in I 2 S Mode)
569
SPI RX CRC Register (SPI_CRCRDAT) (Not Used in I 2 S Mode)
569
SPI TX CRC Register (SPI_ CRCTDAT)
569
SPI_I 2 S Configuration Register (SPI_I2SCFG)
570
SPI_I2S Prescaler Register (SPI_I2SPREDIV)
571
Controller Area Network (CAN)
573
Introduction to CAN
573
Main Features of CAN
573
CAN Overall Introduction
573
CAN Module
574
CAN Working Mode
574
Figure 25-1 Topology of CAN Network
574
Send Mailbox
576
Receiving Filter
576
Receive FIFO
576
Figure 25-2 CAN Working Mode
576
CAN Test Mode
577
Figure 25-3 Single CAN Block Diagram
577
Figure 25-4 Loopback Mode
578
Figure 25-5 Silent Mode
579
CAN Debugging Mode
580
CAN Function Description
580
Send Processing
580
Figure 25-6 Loopback Silent Mode
580
Time Triggered Communication Mode
581
Non-Automatic Retransmission Mode
581
Receiving Management
582
Figure 25-7 Send Mailbox Status
582
Figure 25-8 Receive FIFO Status
583
Identifier Filtering
584
Figure 25-9 Filter Bit Width Setting-Register Organization
585
Table 25-1 Examples of Filter Numbers
586
Message Storage
587
Table 25-2 Send Mailbox Register List
587
Figure 25-10 Examples of Filter Mechanisms
587
Bit Time Characteristic
588
Table 25-3 Receive Mailbox Register List
588
Figure 25-11 Bit Sequence
589
Figure 25-12 Various CAN Frames
590
CAN Interrupt
591
Figure 25-13 Event Flag and Interrupt Generation
591
Error Management
592
Bus-Off Recovery
592
Figure 25-14 CAN Error State Diagram
592
CAN Configuration Flow
593
CAN Registers
594
Register Description
594
CAN Register Overview
595
Table 25-4 CAN Register Overview
595
CAN Control and Status Register
598
CAN Mailbox Register
609
CAN Filter Register
614
Universal Serial Bus Full-Speed Device Interface (Usb_Fs_Device)
619
Introduction
619
Main Features
619
Clock Configuration
620
Functional Description
620
Figure 26-1 USB Device Block Diagram
620
Access Packet Buffer Memory
621
Buffer Description Table
622
Figure 26-2 the User Applications on the Microcontrollers and the USB Modules Access Packet Buffer Memory
622
Double-Buffered Endpoints
623
Figure 26-3 the Relationship between the Buffer Description Table and the Endpoint Packet Buffer
623
Table 26-1 DATTOG and SW_BUF Definitions
624
Table 26-2 How to Use Double Buffering
624
Figure 26-4 Double Buffered Bulk Endpoint Example
625
USB Transfer
626
Figure 26-5 Control Transfer
629
USB Events and Interrupts
630
Table 26-3 How to Use Isochronous Double Buffering
630
Endpoint Initialization
632
USB Registers
632
Table 26-4 Resume Event Detection
632
USB Register Overview
633
Table 26-5 USB Register Overview
633
USB Endpoint N Register (Usb_Epn), N=[0
634
Table 26-6 Receive Status Code
636
Table 26-7 Send Status Code
636
USB Control Register (USB_CTRL)
637
USB Interrupt Status Register (USB_STS)
639
USB Frame Number Register (USB_FN)
641
USB Device Address Register (USB_ADDR)
642
USB Packet Buffer Description Table Address Register (USB_BUFTAB)
642
Buffer Description Table
642
Send Buffer Address Register N (Usb_Addrn_Tx)
643
Send Data Byte Number Register N (Usb_Cntn_Tx)
643
Receive Buffer Address Register N (Usb_Addrn_Rx)
643
Receive Data Byte Number Register N (Usb_Cntn_Rx)
644
Table 26-8 Endpoint Packet Receive Buffer Size Definition
644
Debug Support (DBG)
646
Overview
646
Figure 27-1 N32G43X Level and Cortex
646
TM -M4F Level Debugging Block Diagram
646
JTAG/SWD Function
647
Switch JTAG/SWD Interface
647
Pin Allocation
647
MCU Debug Function
648
Low-Power Mode Debug Support
648
Table 27-1 Debug Port Pin
648
Peripherals Debug Support
649
DBG Registers
649
DBG Register Overview
649
ID Register (DBG_ID)
649
Table 27-2 DBG Register Overview
649
Debug Control Register (DBG_CTRL)
650
Unique Device Serial Number (UID)
652
Introduction
652
UID Register
652
UCID Register
652
Version History
653
Notice
654
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