Nations N32G031 Series Manuals

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Nations N32G031 Series User Manual

Nations N32G031 Series User Manual (557 pages)

32-bit ARM Cortex-M0 microcontroller

Brand: Nations | Category: Microcontrollers | Size: 8 MB

Table of Contents

Table of Contents
2
Abbreviations in the Text
27
List of Abbreviations for Registers
27
Available Peripherals
27
Memory and Bus Architecture
28
System Architecture
28
Bus Architecture
28
Figure 2-1 Bus Architecture
29
Bus Address Mapping
30
Figure 2-2 Bus Address Map
30
Table 2-1 List of Peripheral Register Addresses
31
Boot Management
32
Embedded Boot Loader
33
Memory System
33
FLASH Specification
33
Table 2-2 List of Boot Mode
33
Table 2-3 Flash Bus Address List
34
Option Byte
37
Table 2-4 Option Byte List
38
Write Protect
39
Table 2-5 Read Protection Configuration List
39
Table 2-6 Flash Read-Write-Erase
41
Sram
45
FLASH Register Description
46
Table 2-7 FLASH Register Overview
46
Power Control (PWR)
53
General Description
53
Power Supply
53
Power Supply Supervisor
54
Figure 3-1 Power Supply Block Diagram
54
Figure 3-2 Power on Reset/Power down Reset Waveform
55
Programmable Voltage Detector (PVD)
55
Nrst
56
Power Modes
56
Table 3-1 Power Modes
56
Figure 3-3 PVD Threshold Diagram
56
Table 3-2 Peripheral Running Status
57
LPRUN Mode
58
SLEEP Mode
59
Enter SLEEP Mode
59
Exit SLEEP Mode
59
STOP Mode
59
PD Mode
60
Debug Support
61
Low Power Mode Debug Support
61
Peripheral Debug Support
61
PWR Registers
61
PWR Register Overview
61
Table 3-3 PWR Register Overview
61
Power Control Register (PWR_CTRL)
62
Power Control Status Register (PWR_CTRLSTS)
63
Power Control Register 2 (PWR_CTRL2)
65
Power Control Register 3 (PWR_CTRL3)
65
Power Control Register 4 (PWR_CTRL4)
65
Power Control Register 5 (PWR_CTRL5)
66
Power Control Register 6 (PWR_CTRL6)
67
Debug Control Register (DBG_CTRL)
67
Reset and Clock Control (RCC)
70
Reset Control Unit
70
Power Reset
70
System Reset
70
Software Reset
71
Low-Power Management Reset
71
Clock Control Unit
72
Figure 4-1 System Reset Generation
72
Clock Tree Diagram
74
Figure 4-2 Clock Tree
74
HSE Clock
75
Figure 4-3 HSE Clock Source
75
External Crystal/Ceramic Resonator (HSE Crystal)
75
HSI Clock
76
PLL Clock
76
LSE Clock
77
LSI Clock
77
Figure 4-4 PLL Clock Configuration
77
System Clock (SYSCLK) Selection
78
Clock Security System (CLKSS)
78
RTC Clock
78
Watchdog Clock
78
LPUART Clock
78
LPTIME Clock
79
Clock Output(MCO)
79
RCC Registers
79
RCC Register Overview
79
Table 4-1 RCC Register Overview
79
Clock Control Register (RCC_CTRL)
81
Clock Configuration Register (RCC_CFG)
82
Clock Interrupt Register (RCC_CLKINT)
85
APB2 Peripheral Reset Register (RCC_APB2PRST)
88
APB1 Peripheral Reset Register (RCC_APB1PRST)
89
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
90
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
92
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
93
Low Speed Clock Control Register (RCC_LSCTRL)
95
Control/Status Register (RCC_CTRLSTS)
96
AHB Peripheral Reset Register (RCC_AHBPRST)
98
Clock Configuration Register 2(RCC_CFG2)
99
Table 5-25 ADC
100
EMC Control Register 3 (RCC_EMCCTRL)
101
GPIO and AFIO
104
Summary
104
Function Description
105
I/O Mode Configuration
105
Table 5-1 I/O Port Configuration Table
105
Figure 5-1 Basic Structure of I/O Ports
105
Table 5-2 I/O List of Functional Features of the Pin
106
Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode
107
Figure 5-3 Output Mode
108
Figure 5-4 Alternate Function Mode
109
Figure 5-5 Analog Function Mode with High Impedance
109
Status after Reset
110
Individual Bit Setting and Bit Clearing
110
External Interrupt /Wakeup Line
110
Alternate Function
110
Table 5-3 I/O List of Functional Features of the Pin
111
Table 5-4 TIM1 Alternate Function I/O Remapping
111
Table 5-5 TIM8 Alternate Function I/O Remapping
112
Table 5-6 TIM3 Alternate Function I/O Remapping
112
Table 5-7 LPTIM Alternate Function I/O Remapping
113
Table 5-8 USART1 Alternate Function I/O Remapping
113
Table 5-9 USART2 Alternate Function I/O Remapping
114
Table 5-10 LPUART Alternate Function I/O Remapping
114
Table 5-11 I2C1 Alternate Function I/O Remapping
115
Table 5-12 I2C2 Alternate Function I/O Remapping
115
Table 5-13 SPI1/I2S Alternate Function I/O Remapping
116
Table 5-14 SPI2 Alternate Function I/O Remapping
117
Table 5-15 COMP Alternate Function I/O Remapping
117
Table 5-16 BEEPER Alternate Function I/O Remapping
117
Table 5-17 EVENTOUT Alternate Function I/O Remapping
117
Table 5-18 RTC Alternate Function I/O Remapping
118
Table 5-19 RCC Alternate Function I/O Remapping
118
Table 5-20 OSC_IN/OSC_OUT Alternate Function I/O Remapping
118
Table 5-21 OSC32 Alternate Function Remapping
119
Table 5-22 OSC Alternate Function Remapping
119
Table 5-23 ADC External Trigger Injection Conversion Alternate Function Remapping
119
I/O Configuration of Peripherals
120
Table 5-24 ADC External Trigger Regular Conversion Alternate Function Remapping
120
Table 5-26 PVD
120
Table 5-27 TIM1/TIM8
120
Table 5-28 TIM3 and LPTIM
120
Table 5-29 USART
120
Table 5-30 LPUART
121
Table 5-31 I2C
121
Table 5-32 SPI
121
Table 5-33 COMP
121
GPIO Locking Mechanism
122
Table 5-34 BEEPER
122
Table 5-35 Other
122
GPIO Registers
123
GPIO Register Overview
123
Table 5-36 GPIO Register Overview
123
GPIO Port Mode Description Register (Gpiox_Pmode)
124
GPIO Port Type Definition (Gpiox_Potype)
125
GPIO Slew Rate Configuration Register (Gpiox_Sr)
125
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupd)
126
GPIO Port Input Data Register (Gpiox_Pid)
127
GPIO Port Output Data Register (Gpiox_Pod)
127
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)
128
GPIO Port Configuration Lock Register (Gpiox_ PLOCK)
129
GPIO Alternate Function Low Register (Gpiox_Afl)
129
GPIO Alternate Function High Register (Gpiox_Afh)
130
GPIO Port Bit Clear Register (Gpiox_Pbc)
131
GPIO Driver Strength Configuration Register (Gpiox_ DS)
132
AFIO Registers
132
AFIO Register Overview
132
Table 5-37 AFIO Register Overview
132
AFIO Configuration Register (AFIO_CFG)
133
AFIO External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1)
134
AFIO External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2)
134
AFIO External Interrupt Configuration Register 3 (AFIO_EXTI_CFG3)
135
AFIO External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4)
136
Interrupts and Events
137
Nested Vectored Interrupt Controller
137
Systick Calibration Value Register
137
Interrupt and Exception Vectors
137
Table 6-1 Vector Table
137
External Interrupt/Event Controller (EXTI)
140
Introduction
140
Main Features
140
Functional Description
141
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram
141
EXTI Line Mapping
143
Figure 6-2 External Interrupt Generic I/O Mapping
143
EXTI Registers
145
EXTI Register Overview
145
Interrupt Mask Register(EXTI_IMASK)
145
Table 6-2 EXTI Register Overview
145
Event Mask Register(EXTI_EMASK)
146
Rising Edge Trigger Selection Register(EXTI_RT_CFG)
146
Falling Edge Trigger Selection Register(EXTI_FT_CFG)
147
Software Interrupt Enable Register(EXTI_SWIE)
147
Interrupt Request Pending Register(EXTI_PEND)
148
RTC Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
149
DMA Controller
150
Introduction
150
Main Features
150
Block Diagram
151
Function Description
151
DMA Operation
151
Figure 7-1 DMA Block Diagram
151
Channel Priority and Arbitration
152
DMA Channels and Number of Transfers
152
Programmable Data Bit Width, Alignment and Endians
152
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
152
Peripheral/Memory Address Incrementation
154
Channel Configuration Procedure
154
Flow Control
155
Circular Mode
155
Table 7-2 Flow Control Table
155
Error Management
156
Interrupt
156
DMA Request Mapping
156
Table 7-3 DMA Interrupt Request
156
DMA Registers
157
DMA Register Overview
157
Table 7-4 DMA Request Mapping
157
Table 7-5 DMA Register Overview
157
DMA Interrupt Status Register (DMA_INTSTS)
158
DMA Interrupt Flag Clear Register (DMA_INTCLR)
159
DMA Channel X Configuration Register (Dma_Chcfgx)
160
DMA Channel X Transfer Number Register (Dma_Txnumx)
162
DMA Channel X Peripheral Address Register (Dma_Paddrx)
162
DMA Channel X Memory Address Register (Dma_Maddrx)
163
DMA Channel X Channel Request Select Register (Dma_Chselx)
163
CRC Calculation Unit
165
CRC Introduction
165
CRC Main Features
165
CRC32 Module
165
CRC16 Module
165
CRC Function Description
166
Crc32
166
Crc16
166
Figure 8-1 CRC Calculation Unit Block Diagram
166
CRC Registers
167
CRC Register Overview
167
CRC32 Data Register (CRC_CRC32DAT)
167
CRC32 Independent Data Register (CRC_CRC32IDAT)
167
Table 8-1 CRC Register Overview
167
CRC32 Control Register (CRC_CRC32CTRL)
168
CRC16 Control Register (CRC_CRC16CTRL)
168
CRC16 Input Data Register (CRC_CRC16DAT)
169
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
169
LRC Result Register (CRC_LRC)
170
Advanced-Control Timers (TIM1 and TIM8)
171
TIM1 and TIM8 Introduction
171
Main Features of TIM1 and TIM8
171
TIM1 and TIM8 Function Description
172
Time-Base Unit
172
Figure 9-1 Block Diagram of TIM1 and TIM8
172
Prescaler Description
173
Counter Mode
173
Figure 9-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
173
Up-Counting Mode
173
Figure 9-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
175
Down-Counting Mode
177
Figure 9-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
177
Center-Aligned Mode
177
Figure 9-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
178
Figure 9-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
179
Counter Underflow
179
Repetition Counter
179
Figure 9-8 Repeat Count Sequence Diagram in Down-Counting Mode
180
Figure 9-9 Repeat Count Sequence Diagram in Up-Counting Mode
181
Figure 9-10 Repeat Count Sequence Diagram in Center-Aligned Mode
181
Clock Selection
182
Figure 9-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
182
Figure 9-12 TI2 External Clock Connection Example
183
Figure 9-13 Control Circuit in External Clock Mode 1
184
Figure 9-14 External Trigger Input Block Diagram
184
Capture/Compare Channels
185
Figure 9-15 Control Circuit in External Clock Mode 2
185
Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
186
Figure 9-17 Capture/Compare Channel 1 Main Circuit
187
Figure 9-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
187
Input Capture Mode
188
Figure 9-19 Output Part of Channelx (X= 4)
188
PWM Input Mode
189
Forced Output Mode
190
Figure 9-20 PWM Input Mode Timing
190
Output Compare Mode
191
PWM Mode
192
PWM Center-Aligned Mode
192
Figure 9-21 Output Compare Mode, Toggle on OC1
192
Figure 9-22 Center-Aligned PWM Waveform (AR=8)
193
Figure 9-23 Edge-Aligned PWM Waveform (APR=8)
194
One-Pulse Mode
195
Figure 9-24 Example of One-Pulse Mode
195
Clearing the Ocxref Signal on an External Event
196
Complementary Outputs with Dead-Time Insertion
197
Figure 9-25 Clearing the Ocxref of Timx
197
Figure 9-26 Complementary Output with Dead-Time Insertion
198
Break Function
199
Debug Mode
201
Timx and External Trigger Synchronization
201
Slave Mode: Reset Mode
201
Figure 9-27 Output Behavior in Response to a Break
201
Slave Mode: Trigger Mode
202
Figure 9-28 Control Circuit in Reset Mode
202
Slave Mode: Gated Mode
203
Figure 9-29 Control Circuit in Trigger Mode
203
Figure 9-30 Control Circuit in Gated Mode
204
Timer Synchronization
205
6-Step PWM Generation
205
Figure 9-31 Control Circuit in Trigger Mode + External Clock Mode2
205
Encoder Interface Mode
206
Figure 9-32 6-Step PWM Generation, COM Example (OSSR=1)
206
Table 9-1 Counting Direction Versus Encoder Signals
207
Figure 9-33 Example of Counter Operation in Encoder Interface Mode
207
Figure 9-34 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
208
Interfacing with Hall Sensor
209
Figure 9-35 Example of Hall Sensor Interface
210
Timx Register Description(X=1, 8)
211
Register Overview
211
Table 9-2 Register Overview
211
Control Register 1 (Timx_Ctrl1)
212
Control Register 2 (Timx_Ctrl2)
214
Slave Mode Control Register (Timx_Smctrl)
216
Table 9-3 Timx Internal Trigger Connection
218
Dma/Interrupt Enable Registers (Timx_Dinten)
219
Status Registers (Timx_Sts)
220
Event Generation Registers (Timx_Evtgen)
222
Capture/Compare Mode Register 1 (Timx_Ccmod1)
223
Capture/Compare Mode Register 2 (Timx_Ccmod2)
227
Capture/Compare Enable Registers (Timx_Ccen)
228
Table 9-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
230
Counters (Timx_Cnt)
231
Prescaler (Timx_Psc)
231
Auto-Reload Register (Timx_Ar)
232
Repeat Count Registers (Timx_Repcnt)
232
Capture/Compare Register 1 (Timx_Ccdat1)
233
Capture/Compare Register 2 (Timx_Ccdat2)
233
Capture/Compare Register 3 (Timx_Ccdat3)
234
Capture/Compare Register 4 (Timx_Ccdat4)
234
Break and Dead-Time Registers (Timx_Bkdt)
235
DMA Control Register (Timx_Dctrl)
237
DMA Transfer Buffer Register (Timx_Daddr)
237
Capture/Compare Mode Registers 3(Timx_Ccmod3)
238
Capture/Compare Register 5 (Timx_Ccdat5)
239
Capture/Compare Register 6 (Timx_Ccdat6)
239
General-Purpose Timers (TIM3)
240
General-Purpose Timers Introduction
240
Main Features of General-Purpose Timers
240
General-Purpose Timers Description
241
Time-Base Unit
241
Figure 10-1 Block Diagram of Timx（X=3
241
Counter Mode
242
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
242
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
243
Figure 9-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
244
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
244
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
245
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
246
Clock Selection
247
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
247
Figure 10-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
248
Figure 10-9 TI2 External Clock Connection Example
249
Figure 10-10 Control Circuit in External Clock Mode 1
250
Figure 10-11 External Trigger Input Block Diagram
250
Capture/Compare Channels
251
Figure 10-12 Control Circuit in External Clock Mode 2
251
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
252
Figure 10-14 Capture/Compare Channel 1 Main Circuit
253
Input Capture Mode
254
Figure 10-15 Output Part of Channelx （X = 1,2,3,4;Take Channel 4 as an Example
254
PWM Input Mode
255
Forced Output Mode
256
Output Compare Mode
256
Figure 10-16 PWM Input Mode Timing
256
PWM Mode
258
Figure 10-17 Output Compare Mode, Toggle on OC1
258
Figure 10-18 Center-Aligned PWM Waveform (AR=8)
259
Figure 10-19 Edge-Aligned PWM Waveform (APR=8)
260
One-Pulse Mode
261
Figure 10-20 Example of One-Pulse Mode
261
Clearing the Ocxref Signal on an External Event
262
Debug Mode
263
Timx and External Trigger Synchronization
263
Timer Synchronization
263
Figure 10-21 Control Circuit in Reset Mode
263
Figure 10-22 Block Diagram of Timer Interconnection
264
Figure 10-23 TIM3 Gated by OC1REF of TIM1
265
Figure 10-24 TIM3 Gated by Enable Signal of TIM1
266
Figure 10-25 Trigger TIM3 with an Update of TIM1
267
Encoder Interface Mode
268
Table 10-1 Counting Direction Versus Encoder Signals
268
Figure 10-26 Triggers Timers 1 and 3 Using the TI1 Input of TIM1
268
Figure 10-27 Example of Counter Operation in Encoder Interface Mode
269
Interfacing with Hall Sensor
270
Timx Register Description(X=3)
270
Register Overview
270
Table 10-2 Register Overview
270
Control Register 1 (Timx_Ctrl1)
272
Control Register 2 (Timx_Ctrl2)
274
Slave Mode Control Register (Timx_Smctrl)
275
Dma/Interrupt Enable Registers (Timx_Dinten)
277
Table 10-3 Timx Internal Trigger Connection
277
Status Registers (Timx_Sts)
278
Event Generation Registers (Timx_Evtgen)
280
Capture/Compare Mode Register 1 (Timx_Ccmod1)
281
Capture/Compare Mode Register 2 (Timx_Ccmod2)
284
Capture/Compare Enable Registers (Timx_Ccen)
286
Counters (Timx_Cnt)
287
Table 10-4 Output Control Bits of Standard Ocx Channel
287
Prescaler (Timx_Psc)
288
Auto-Reload Register (Timx_Ar)
288
Capture/Compare Register 1 (Timx_Ccdat1)
288
Capture/Compare Register 2 (Timx_Ccdat2)
289
Capture/Compare Register 3 (Timx_Ccdat3)
289
Capture/Compare Register 4 (Timx_Ccdat4)
290
DMA Control Register (Timx_Dctrl)
290
DMA Transfer Buffer Register (Timx_Daddr)
291
Basic Timers (TIM6)
293
Basic Timers Introduction
293
Main Features of Basic Timers
293
Basic Timers Description
293
Time-Base Unit
293
Figure 11-1 Block Diagram of Timx（X = 6
293
Counter Mode
294
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
294
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
295
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
296
Clock Selection
297
Debug Mode
297
Timx Register Description(X=6)
297
Figure 11-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
297
Register Overview
298
Control Register 1 (Timx_Ctrl1)
298
Table 11-1 Register Overview
298
Dma/Interrupt Enable Registers (Timx_Dinten)
299
Status Registers (Timx_Sts)
300
Event Generation Registers (Timx_Evtgen)
300
Counters (Timx_Cnt)
301
Prescaler (Timx_Psc)
301
Automatic Reload Register (Timx_Ar)
302
Low Power Timer (LPTIM)
303
Introduction
303
Main Features
303
Block Diagram
304
Function Description
304
LPTIM Clocks and On-Off Control
304
Figure 12-1 LPTIM Diagram
304
Prescaler
305
Glitch Filter
305
Table 12-1 Pre-Scaler Division Ratios
305
Timer Enable
306
Trigger Multiplexer
306
Figure 12-2 Glitch Filter Timing Diagram
306
Operating Mode
307
Table 12-2 6 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits
307
Figure 12-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
308
Figure 12-4 PTIM Output Waveform, Single Counting Mode Configuration
309
Figure 12-5 LPTIM Output Waveform, Single Counting Mode Configuration and Set-Once Mode Activated
309
Waveform Generation
310
Register Update
311
Figure 12-6 Waveform Generation
311
Counter Mode
312
Encoder Mode
312
Non-Orthogonal Encoder Mode
314
Figure 12-7 Encoder Mode Counting Sequence
314
Timeout Function
315
Figure 12-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally
315
Figure 12-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working
315
LPTIM Interrupts
316
LPTIM Registers
316
LPTIM Register Overview
316
LPTIM Interrupt and Status Register (LPTIM_INTSTS)
317
LPTIM Interrupt Clear Register (LPTIM_INTCLR)
318
LPTIM Interrupt Enable Register (LPTIM_INTEN)
319
LPTIM Configuration Register (LPTIM_CFG)
320
LPTIM Control Register (LPTIM_CTRL)
323
LPTIM Compare Register (LPTIM_COMP)
323
LPTIM Auto-Reload Register (LPTIM_ARR)
324
LPTIM Counter Register (LPTIM_CNT)
324
Independent Watchdog (IWDG)
326
Introduction
326
Main Features
326
Function Description
327
Register Access Protection
327
Figure 13-1 Functional Block Diagram of the Independent Watchdog Module
327
Debug Mode
328
User Interface
328
Operate Flow
328
IWDG Registers
329
IWDG Register Overview
329
IWDG Key Register (IWDG_KEY)
329
Table 13-1 IWDG Counting Maximum and Minimum Reset Time
329
Table 13-2 IWDG Register Overview
329
IWDG Pre-Scaler Register (IWDG_PREDIV)
330
IWDG Reload Register (IWDG_RELV)
330
IWDG Status Register (IWDG_STS)
331
Window Watchdog (WWDG)
332
Introduction
332
Main Features
332
Function Description
332
Figure 14-1 Watchdog Block Diagram
332
Timing for Refresh Watchdog and Interrupt Generation
333
Figure 14-2 Refresh Window and Interrupt Timing of WWDG
333
Debug Mode
334
User Interface
334
WWDG Configuration Flow
334
Table 14-1 Maximum and Minimum Counting Time of WWDG
334
WWDG Registers
335
WWDG Register Overview
335
WWDG Control Register (WWDG_CTRL)
335
WWDG Config Register (WWDG_CFG)
335
Table 14-2 WWDG Register Overview
335
WWDG Status Register (WWDG_STS)
336
Analog to Digital Conversion (ADC)
337
Introduction
337
Main Features
337
Function Description
338
Table 15-1 ADC Pins
338
Figure 15-1 Block Diagram of a Single ADC
338
ADC Clock
339
ADC Switch Control
340
Channel Selection
340
Figure 15-2 ADC Clock
340
Internal Channel
341
Single Conversion Mode
341
Continuous Conversion Mode
341
Timing Diagram
342
Analog Watchdog
342
Figure 15-3 Timing Diagram
342
Scan Mode
343
Injection Channel Management
343
Table 15-2 Analog Watchdog Channel Selection
343
Discontinuous Mode
344
Figure 15-4 Injection Conversion Delay
344
Data Aligned
345
Programmable Channel Sampling Time
345
Table 15-3 Right-Align Data
345
Table 15-4 Left-Aligne Data
345
Externally Triggered Conversion
346
Table 15-5 ADC Is Used for External Triggering of Regular Channels
346
Table 15-6 ADC Is Used for External Triggering of Injection Channels
346
DMA Requests
347
Temperature Sensor
347
Temperature Sensor Using Flow
348
Figure 15-5 Temperature Sensor and VREFINT Diagram of the Channel
348
ADC Interrupt
349
OPA Channel Control
349
Table 15-7 ADC Interrupt
349
Figure 15-6 TIM1 CC4 Triggers OPA Channel Switching ADC Injection Sampling
349
Table 15-8 OPA Channel Selection
350
ADC Registers
351
ADC Register Overview
351
Table 15-9 ADC Register Overview
351
ADC Status Register (ADC_STS)
352
ADC Control Register 1 (ADC_CTRL1)
353
ADC Control Register 2 (ADC_CTRL2)
355
ADC Sampling Time Register 1 (ADC_SAMPT1)
357
ADC Sampling Time Register 2 (ADC_ SAMPT2)
358
ADC Sampling Time Register 3 (ADC_SAMPT3)
358
ADC Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1
360
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
360
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
360
ADC Regular Sequence Register 1 (ADC_RSEQ1)
361
ADC Regular Sequence Register 2 (ADC_RSEQ2)
362
ADC Regular Sequence Register 3 (ADC_RSEQ3)
362
ADC Injection Sequence Register (ADC_JSEQ)
363
ADC Injection Data Register X (Adc_Jdatx) (X= 1
364
ADC Regulars Data Register (ADC_DAT)
364
ADC Control Register 3 (ADC_CTRL3)
365
ADC Test Register (ADC_TEST)
366
ADC OPA Control Register (ADC_OPACTRL)
366
Comparator (COMP)
368
COMP System Connection Block Diagram
368
COMP Features
368
Figure 16-1 Comparator System Connection Diagram
368
COMP Configuration Process
369
COMP Working Mode
369
Independent Comparator
369
Comparator Interconnection
370
Interrupt
370
COMP Register
371
COMP Register Overview
371
Table 16-1 COMP Register Overview
371
COMP Interrupt Enable Register (COMP_INTEN)
372
COMP Interrupt Register (COMP_INTSTS)
372
COMP Lock Register(COMP_LOCK)
372
COMP Control Register (COMP_CTRL)
373
COMP Filter Control Register (COMP_FILC)
375
COMP Filter Frequency Division Register (COMP_FILP)
375
COMP Reference Input Compare Voltage Register (COMP_INVREF)
376
I2C Interface
377
Introduction
377
Main Features
377
Function Description
377
SDA and SCL Line Control
378
Software Communication Process
378
Figure 17-1 I2C Functional Block Diagram
379
Start and Stop Conditions
379
Figure 17-2 I2C Bus Protocol
379
Clock Synchronization and Arbitration
379
Figure 17-3 Slave Transmitter Transfer Sequence Diagram
382
Figure 17-4 Slave Receiver Transfer Sequence Diagram
383
Figure 17-5 Master Transmitter Transfer Sequence Diagram
385
Figure 17-6 Master Receiver Transfer Sequence Diagram
387
Error Conditions Description
388
DMA Application
389
Transmit Process
389
Receive Process
389
Packet Error Check
390
Smbus
390
Device Identification
391
Bus Protocol
391
Table 17-1 Comparison between Smbus and I2C
391
Address Resolution Protocol
392
Debug Mode
393
Interrupt Request
393
Table 17-2 I 2 C Interrupt Request
393
I2C Registers
394
I2C Register Overview
394
Table 17-3 I2C Register Overview
394
I2C Control Register 1 (I2C_CTRL1)
395
I2C Control Register 2 (I2C_CTRL2)
397
I2C Own Address Register 1 (I2C_OADDR1)
398
I2C Own Address Register 2 (I2C_OADDR2)
399
I2C Data Register (I2C_DAT)
399
I2C Status Register 1 (I2C_STS1)
400
I2C Status Register 2 (I2C_STS2)
403
I2C Clock Control Register (I2C_CLKCTRL)
404
I2C Rise Time Register (I2C_TMRISE)
405
Universal Synchronous Asynchronous Receiver Transmitter (USART)
407
Introduction
407
Main Features
407
Functional Block Diagram
408
Function Description
408
Figure 18-1 USART Block Diagram
408
USART Frame Format
409
Transmitter
410
Figure 18-2 Word Length = 8 Setting
410
Figure 18-3 Word Length = 9 Setting
410
Table 18-1 Stop Bit Configuration
411
Figure 18-4 Configuration Stop Bit
411
Single Byte Communication
412
Receiver
413
Start Bit Detection
413
Figure 18-5 TXC/TXDE Changes During Transmission
413
Figure 18-6 Start Bit Detection
414
Framing Error
416
Overrun Error
416
Table 18-2 Data Sampling for Noise Detection
416
Generation of Fractional Baud Rate
417
Receiver's Tolerance Clock Deviation
418
Table 18-3 Error Calculation When Setting Baud Rate
418
Parity Control
419
Table 18-4 When Div_Decimal = 0. Tolerance of USART Receiver
419
Table 18-5 When Div_Decimal != 0. Tolerance of USART Receiver
419
Table 18-6 Frame Format
419
DMA Application
420
Figure 18-7 Transmission Using DMA
421
Hardware Flow Control
422
Figure 18-8 Reception Using DMA
422
Figure 18-9 Hardware Flow Control between Two USART
423
Figure 18-10 RTS Flow Control
423
Multiprocessor Communication
424
Idle Line Detection
424
Figure 18-11 CTS Flow Controls
424
Figure 18-12 Mute Mode Using Idle Line Detection
425
Synchronous Mode
426
Figure 18-13 Mute Mode Detected Using Address Mark
426
Figure 18-14 USART Synchronous Transmission Example
427
Figure 18-15 USART Data Clock Timing Example (WL=0)
428
Figure 18-16 USART Data Clock Timing Example (WL=1)
429
Figure 18-17 RX Data Sampling / Holding Time
429
Single-Wire Half-Duplex Mode
430
Irda SIR ENDEC Mode
430
Irda Low Power Mode
431
Figure 18-18 Irdasirendec-Block Diagram
431
LIN Mode
432
Figure 18-19 Irda Data Modulation (3/16)-Normal Mode
432
Figure 18-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
433
Smartcard Mode (ISO7816)
434
Figure 18-21 Break Detection and Framing Error Detection in LIN Mode
434
Figure 18-22 ISO7816-3 Asynchronous Protocol
435
Interrupt Request
436
Table 18-7 USART Interrupt Request
436
Figure 18-23 Use 1.5 Stop Bits to Detect Parity Errors
436
Mode Support
437
USART Register
437
USART Register Overview
437
Table 18-8 USART Mode Setting
437
Table 18-9 USART Register Overview
437
USART Status Register (USART_STS)
438
USART Data Register (USART_DAT)
440
USART Baud Rate Register (USART_BRCF)
441
USART Control Register 1 Register (USART_CTRL1)
441
USART Control Register 2 Register (USART_CTRL2)
443
USART Control Register 3 Register (USART_CTRL3)
444
USART Guard Time and Prescaler Register (USART_GTP)
446
Low Power Universal Asynchronous Receiver Transmitter (LPUART)
448
Introduction
448
Main Features
448
Functional Block Diagram
449
Function Description
449
Figure 19-1 LPUART Block Diagram
449
LPUART Frame Format
450
Transmitter
450
Figure 19-2 Frame Format
450
Receiver
452
Figure 19-3 TXC Changes During Transmission
452
Fractional Baud Rate Generation
454
Table 19-1 Data Sampling for Noise Detection
454
Figure 19-4 Data Sampling for Noise Detection
454
Parity Control
456
DMA Application
456
Table 19-2 Parity Frame Format
456
Figure 19-5 Sending Using DMA
457
Hardware Flow Control
458
Figure 19-6 Receiving with DMA
458
Figure 19-7 Hardware Flow Control between Two LPUART
458
Figure 19-8 RTS Flow Control
459
Low Power Wake up
460
Interrupt Request
460
Table 19-3 LPUART Interrupt Requests
460
Figure 19-9 CTS Flow Control
460
LPUART Registers
461
LPUART Register Overview
461
LPUART Status Register (LPUART_STS)
461
Table 19-4 LPUART Register Overview
461
LPUART Interrupt Enable Register (LPUART_INTEN)
462
LPUART Control Register (LPUART_CTRL)
463
LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1)
464
LPUART Data Register (LPUART_DAT)
465
LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2)
465
LPUART Wake up Data Register (LPUART_WUDAT)
466
Serial Peripheral Interface/Inter-IC Sound (SPI/ I2S)
467
SPI Introduction
467
SPI and I2S Main Features
467
SPI Features
467
I2S Features
467
SPI Function Description
468
General Description
468
Figure 20-1 SPI Block Diagram
468
Figure 20-2 Selective Management of Hardware/Software
469
Figure 20-3 Master and Slave Applications
470
Data Format
471
SPI Work Mode
471
Figure 20-4 Data Clock Timing Diagram
471
Figure 20-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in
472
Figure 20-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode
473
Figure 20-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode
474
Figure 20-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in
475
Figure 20-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit-Only Mode
475
Status Flag
477
Figure 20-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted
477
Turn off the SPI
478
SPI Communication Using DMA
479
CRC Calculation
480
Figure 20-11 Transmission Using DMA
480
Figure 20-12 Reception Using DMA
480
Error Flag
481
CRC Error (CRCERR)
482
SPI Interrupt
482
Table 20-1 SPI Interrupt Request
482
I2S Function Description
483
Figure 20-13 I S Block Diagram
483
Supported Audio Protocols
484
Figure 20-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
485
Figure 20-15 I 2 S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
485
Figure 20-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
487
Figure 20-18 MSB Aligns 24-Bit Data, CLKPOL = 0
487
Figure 20-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
488
Figure 20-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
488
Figure 20-21 LSB Aligns 24-Bit Data, CLKPOL = 0
489
Figure 20-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
489
Figure 20-23 PCM Standard Waveform (16 Bits)
490
Figure 20-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
490
Clock Generator
491
Figure 20-25 I 2 S Clock Generator Structure
491
Figure 20-26 Audio Sampling Frequency Definition
491
I2S Send and Receive Sequence
492
Table 20-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency
492
Status Flag
494
Error Flag
495
I2S Interrupt
495
Table 20-3 I 2 S Interrupt Request
495
DMA Function
496
SPI and I2S Register Description
496
SPI Register Overview
496
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
496
Table 20-4 SPI Register Overview
496
SPI Control Register 2 (SPI_CTRL2)
499
SPI Status Register (SPI_STS)
500
SPI Data Register (SPI_DAT)
501
SPI CRC Polynomial Register (SPI_CRCPOLY) (Not Used in I2S Mode)
501
SPI RX CRC Register (SPI_CRCRDAT) (Not Used in I2S Mode)
502
SPI TX CRC Register（Spi_ CRCTDAT
502
SPI_ I2S Configuration Register（Spi_I2Scfg
503
SPI_I2S Prescaler Register (SPI_I2SPREDIV)
504
Real-Time Clock (RTC)
506
Description
506
Specification
506
Table 21-1 RTC Feature Support
506
RTC Function Description
508
RTC Block Diagram
508
Figure 21-1 RTC Block Diagram
508
Gpios of RTC
509
RTC Register Write Protection
509
RTC Clock and Prescaler
509
RTC Calendar
510
Calendar Initialization and Configuration
510
Calendar Reading
511
Calibration Clock Output
511
Programmable Alarms
512
Alarm Configuration
512
Alarm Output
512
Periodic Automatic Wakeup
512
Wakeup Timer Configuration
513
Timestamp Function
513
Tamper Detection
514
Daylight Saving Time Configuration
515
RTC Sub-Second Register Shift
515
RTC Digital Clock Precision Calibration
515
RTC Low Power Mode
516
RTC Registers
517
RTC Register Overview
517
Table 21-2 RTC Register Overview
517
RTC Calendar Time Register (RTC_TSH)
518
RTC Calendar Date Register (RTC_DATE)
518
RTC Control Register (RTC_CTRL)
519
RTC Initial Status Register (RTC_INITSTS)
521
RTC Prescaler Register (RTC_PRE)
524
RTC Wakeup Timer Register (RTC_WKUPT)
524
RTC Alarm a Register (RTC_ALARMA)
525
RTC Alarm B Register (RTC_ ALARMB)
526
RTC Write Protection Register (RTC_WRP)
527
RTC Sub-Second Register (RTC_SUBS)
527
RTC Shift Control Register (RTC_SCTRL)
527
RTC Timestamp Time Register (RTC_TST)
528
RTC Timestamp Date Register (RTC_TSD)
529
RTC Timestamp Sub-Second Register (RTC_TSSS)
529
RTC Calibration Register (RTC_CALIB)
530
RTC Tamper Configuration Register（Rtc_Tmpcfg
531
RTC Alarm a Sub-Second Register (RTC_ALRMASS)
533
RTC Alarm B Sub-Second Register (RTC_ALRMBSS)
534
Operational Amplifier (OPAMP)
535
OPAMP Features
535
Voltage Follower
535
OPAMP Function Description
535
Figure 22-1 Block Diagram of OPAMP Connection Diagram
535
OPAMP Working Mode
536
OPAMP Standalone Operational Amplifier Mode
536
ADC Channel
536
OPAMP Follow Mode
537
Figure 22-2 OPAMP Standalone Operational Amplifier Mode
537
OPAMP Internal Programmable Gain (PGA) Mode
538
Figure 22-3 OPAMP Follow Mode
538
OPAMP Independent Write Protection
539
OPAMP TIMER Controls the Switching Mode
539
Figure 22-4 Internal Programmable Gain Mode
539
OPAMP Registers
540
OPAMP Register Overview
540
OPAMP Control Status Register (OPAMP_CS)
540
Table 22-1 OPAMP Register Overview
540
OPAMP Lock Register (OPAMP_LOCK)
541
Beeper
543
Introduction
543
Function Description
543
Beeper Registers
543
Beeper Register Overview
543
Beeper Control Register (BEEPER_CTRL)
543
Table 23-1 Beeper Register Overview
543
Arithmetic Units (HDIV and SQRT)
546
Introduction to HDIV and SQRT
546
HDIV and SQRT Function Description
546
HDIV Registers
546
HDIV Register Overview
546
Table 24-1 HDIV Register Overview
546
HDIV Control Status Register (HDIV_CTRLSTS)
547
HDIV Dividend Register (HDIV_DIVIDEND)
547
HDIV Divisor Register (HDIV_DIVISOR)
548
HDIV Quotient Register (HDIV_QUOTIENT)
548
HDIV Remainder Register (HDIV_REMAINDER)
548
HDIV Divide by Zero Register (HDIV_DIVBY0)
549
SQRT Registers
549
SQRT Register Overview
549
Table 24-2 SQRT Register Overview
549
SQRT Control Status Register (SQRT_CTRLSTS)
550
SQRT Radicand Register (SQRT_RADICAND)
550
SQRT Square Root Register (SQRT_ROOT)
551
Debug Support (DBG)
552
Overview
552
SWD Function
553
Pin Assignment
553
Unique Device Serial Number (UID)
554
Introduction
554
UID Register
554
UCID Register
554
DBGMCU_ID Register
554
Table 26-1 DBGMCU_ID Bit Description
554
Version History
556
Notice
557

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