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Nations N32G45 Series Manuals
Manuals and User Guides for Nations N32G45 Series. We have
1
Nations N32G45 Series manual available for free PDF download: User Manual
Nations N32G45 Series User Manual (838 pages)
32-bit ARM Cortex-M4 microcontroller
Brand:
Nations
| Category:
Microcontrollers
| Size: 14.85 MB
Table of Contents
Table of Contents
2
Abbreviations in the Text
36
List of Abbreviations for Registers
36
Available Peripherals
36
Interrupts and Events
37
Nested Vectored Interrupt Controller
37
Systick Calibration Value Register
37
Interrupt and Exception Vectors
37
Table 2-1 Vector Table
37
External Interrupt/Event Controller (EXTI)
40
Introduction
40
Main Features
40
Functional Description
41
Figure 2-1 External Interrupt/Event Controller Block Diagram
41
EXTI Line Mapping
42
Figure 2-2 External Interrupt GPIO Mapping
43
EXTI Registers
44
EXTI Register Review
44
EXTI Interrupt Mask Register (EXTI_IMASK)
44
Table 2-2 EXTI Register Review
44
EXTI Event Mask Register (EXTI_EMASK)
45
Rising Trigger Selection Register (EXTI_RT_CFG)
45
Falling Trigger Selection Register (EXTI_FT_CFG)
45
EXTI Software Interrupt Event Register (EXTI_SWIE)
46
EXTI Pending Register (EXTI_PEND)
46
EXTI Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
47
Memory and Bus Architecture
48
System Architecture
48
Bus Architecture
48
Figure 3-1 Bus Architecture
48
Bus Address Mapping
49
Figure 3-2 Bus Address Map
50
Boot Management
51
Memory System
52
FLASH Specification
52
Table 3-1 List of Boot Mode
52
Table 3-2 Flash Bus Address List
53
Table 3-3 Option Byte List
57
Table 3-4 Read Protection Configuration List
58
Table 3-5 Flash Read-Write-Erase (1) Permission Control Table
60
Icache
64
Sram
65
R-Sram(Retention SRAM
66
Table 3-6 SRAM Capacity Configuration Table
66
FLASH Register
67
Table 3-7 FLASH Register Overview
67
Power Control (PWR)
76
General Description
76
Power Supply
76
Power Supply Supervisor
78
Figure 4-1 Power Supply Block Diagram
78
Figure 4-2 Waveforms of Power-On Reset and Power-Down Reset
79
Power Modes
80
Table 4-1 Power Modes
80
Figure 4-3 PVD Threshold Waveform
80
SLEEP Mode
84
STOP0 Mode
85
STOP2 Mode
86
STANDBY Mode
87
VBAT Mode
87
Low-Power Auto-Wakeup(Awu)Mode
88
PWR Registers
88
PWR Register Overview
88
Table 4-3 PWR Register Overview
88
Power Control Register (PWR_CTRL)
89
Power Control Status Register(PWR_CTRLSTS)
90
Power Control Register 2 (PWR_CTRL2)
91
Power Control Register 3 (PWR_CTRL3)
92
Backup Registers (BKP)
94
Introduction
94
Main Features
94
Function Description
94
BKP Registers
95
BKP Register Overview
95
Table 5-1 BKP Register Overview
95
Backup Data Register X (Bkp_Datx) (X = 1
97
Backup Control Register (BKP_CTRL)
97
Backup Control/Status Register (BKP_CTRLSTS)
98
Reset and Clock Control (RCC)
100
Reset Control Unit
100
Power Reset
100
System Reset
100
Backup Domain Reset
101
Figure 6-1 System Reset Generation
101
Clock Control Unit
102
Clock Tree Diagram
103
HSE Clock
103
Figure 6-2 Clock Tree
103
HSI Clock
104
Figure 6-3 HSE/LSE Clock Source
104
PLL Clock
105
LSE Clock
105
LSI Clock
105
System Clock (SYSCLK) Selection
106
Clock Security System (CLKSS)
106
RTC Clock
107
Watchdog Clock
107
Clock Output(MCO)
107
RCC Registers
107
RCC Register Overview
108
Table 6-1 RCC Register Overview
108
Clock Control Register (RCC_CTRL)
109
Clock Configuration Register (RCC_CFG)
110
Clock Interrupt Register (RCC_CLKINT)
114
APB2 Peripheral Reset Register (RCC_APB2PRST)
116
APB1 Peripheral Reset Register (RCC_APB1PRST)
118
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
120
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
122
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
124
Backup Domain Control Register (RCC_BDCTRL)
127
Clock Control/Status Register (RCC_CTRLSTS)
128
AHB Peripheral Reset Register (RCC_AHBPRST)
130
Clock Configuration Register 2 (RCC_CFG2)
131
Clock Configuration Register 3 (RCC_CFG3)
133
GPIO and AFIO
135
Summary
135
I/O Function Description
136
I/O Mode Configuration
136
Table 7-1 I/O Mode and Configuration Relationship
136
Figure 7-1 Basic Structure of I/O Port
136
Table 7-2 I/O Characteristics of Different I/O Configurations
137
Figure 7-2 Input Float/Pull-Up/Pull-Down Configuration
138
Figure 7-3 Output Mode Configuration
139
Figure 7-4 Alternate Function Configuration
140
Status after Reset
141
Figure 7-5 High Impedance Analog Mode Configuration
141
Individual Bit Setting and Bit Clearing
142
External Interrupt/Wake-Up Line
142
Alternate Function
142
Table 7-3 Debug Port Image
145
Table 7-4 ADC1 External Trigger Injection Conversion Alternate Function Remapping
146
Table 7-5 ADC1 External Trigger Regular Conversion Alternate Function Remapping
146
Table 7-6 ADC2 External Trigger Injection Conversion Alternate Function Remapping
146
Table 7-7 ADC2 External Trigger Regular Conversion Alternate Function Remapping
146
Table 7-8 ADC3 External Trigger Injection Conversion Alternate Function Remapping
147
Table 7-9 ADC3 External Trigger Regular Conversion Alternate Function Remapping
147
Table 7-10 ADC4 External Trigger Injection Conversion Alternate Function Remapping
147
Table 7-11 ADC4 External Trigger Regular Conversion Alternate Function Remapping
147
Table 7-12 TIM5 Alternate Function Remapping
147
Table 7-13 TIM4 Alternate Function Remapping
147
Table 7-14 TIM3 Alternate Function Remapping
147
Table 7-15 TIM2 Alternate Function Remapping
148
Table 7-16 TIM1 Alternate Function Remapping
148
Table 7-17 TIM8 Alternate Function Remapping
148
Table 7-18 CAN1 Alternate Function Remapping
148
Table 7-19 CAN2 Alternate Function Remapping
149
Table 7-20 DVP Alternate Function Remapping
149
Table 7-21 USART1 Alternate Function Remapping
149
Table 7-22 USART2 Alternate Function Remapping
150
Table 7-23 USART3 Alternate Function Remapping
150
Table 7-24 UART4 Alternate Function Remapping
150
Table 7-25 UART5 Alternate Function Remapping
150
Table 7-26 UART6 Alternate Function Remapping
150
Table 7-27 UART7 Alternate Function Remapping
151
Table 7-28 I2C1 Pin Remapping
151
Table 7-29 I2C2 Pin Remapping
151
Table 7-30 I2C3 Pin Remapping
151
Table 7-31 I2C4 Pin Remapping
151
Table 7-32 SPI1 Pin Remapping
152
Table 7-33 SPI2/I2S2 Pin Remapping
152
Table 7-34 SPI3/I2S3 Pin Remapping
152
Table 7-35 SDIO Pin Remapping
152
Table 7-36 QSPI Pin Remapping
153
Table 7-37 ETH Pin Remapping
153
I/O Configuration of Peripherals
154
Table 7-38 ADC/DAC
154
Table 7-39 TIM1/TIM8
154
Table 7-40 TIM2/3/4/5
154
Table 7-41 Bxcan
155
Table 7-42 DVP
155
Table 7-43 USART
155
Table 7-44 I2C
155
Table 7-45 SPI
156
Table 7-46 I2S
156
Table 7-47 SDIO
157
Table 7-48 QSPI
157
Table 7-49 ETH
157
GPIO Locking Mechanism
158
Table 7-50 USB
158
Table 7-51 Other
158
GPIO Registers
159
GPIO Register Overview
159
GPIO Port Low Configuration Register (Gpiox_Pl_Cfg)
160
Table 7-52 GPIO Registers Overview
160
GPIO Port High Configuration Register (Gpiox_Ph_Cfg)
161
GPIO Port Input Data Register (Gpiox_Pid)
162
GPIO Port Output Data Register (Gpiox_Pod)
162
GPIO Port Bit Setting/Clearing Register (Gpiox_Pbsc)
163
GPIO Port Bit Clear Register (Gpiox_Pbc)
163
GPIO Port Lock Configuration Register (Gpiox_Plock_Cfg )
164
GPIO Driver Capability Configuration Register (Gpiox_Ds_Cfg )
165
GPIO Flip Rate Configuration Register (Gpiox_Sr_Cfg)
165
AFIO Registers
166
AFIO Register Overview
166
Table 7-53 AFIO Register Overview
166
AFIO Event Control Register (AFIO_ECTRL)
167
AFIO Alternate Remap Configuration Register (AFIO_RMP_CFG )
167
AFIO External Interrupt Configuration Register 1(AFIO_EXTI_CFG1)
171
AFIO External Interrupt Configuration Register 2(AFIO_EXTI_CFG2)
172
AFIO External Interrupt Configuration Register 3(AFIO_EXTI_CFG3)
172
AFIO External Interrupt Configuration Register 4(AFIO_EXTI_CFG4)
173
AFIO Alternate Remapping Configuration Register 3(AFIO_RMP_CFG3)
174
AFIO Alternate Remap Configuration Register 4 (AFIO_ RMP_CFG4 )
177
AFIO Alternate Remapping Configuration Register 5(AFIO_RMP_CFG5)
180
DMA Controller
183
Introduction
183
Main Features
183
Block Diagram
184
Function Description
184
DMA Operation
184
Figure 8-1 DMA Block Diagram
184
Channel Priority and Arbitration
185
DMA Channels and Number of Transfers
185
Programmable Data Bit Width
185
Table 8-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
186
Peripheral/Memory Address Incrementation
187
Channel Configuration Procedure
187
Flow Control
188
Circular Mode
188
Table 8-2 Flow Control Table
188
Error Management
189
Interrupt
189
DMA Request Mapping
189
Table 8-3 DMA Interrupt Request
189
Table 8-4 DMA1 Request Mapping Table for each Channel
190
Figure 8-2 DMA1 Request Mapping
190
Table 8-5 DMA2 Request Mapping Table for each Channel
192
Figure 8-3 DMA2 Request Mapping
192
DMA Registers
193
DMA Register Overview
193
Table 8-6 DMA Register Overview
193
DMA Interrupt Status Register (DMA_INTSTS)
195
DMA Interrupt Flag Clear Register (DMA_INTCLR)
195
DMA Channel X Configuration Register (Dma_Chcfgx)
196
DMA Channel X Transfer Number Register (Dma_Txnumx)
198
DMA Channel X Peripheral Address Register (Dma_Paddrx)
198
DMA Channel X Memory Address Register (Dma_Maddrx)
199
DMA1 Channel X Channel Request Select Register (Dma1_Chselx)
199
DMA2 Channel X Channel Request Select Register (Dma2_Chselx)
201
DMA Channel MAP Enable Register (DMA_CHMAPEN)
202
Analog to Digital Conversion (ADC)
204
Introduction
204
Main Features
204
Function Description
205
Figure 9-1 Block Diagram of a Single ADC
205
ADC Clock
206
Table 9-1 ADC Pins
206
ADC Switch Control
207
Channel Selection
207
Figure 9-2 ADC Clock
207
Figure 9-3 ADC1 and ADC2 Channel Pin Connections
208
Figure 9-4 ADC3 and ADC4 Channel Pin Connections
210
Internal Channel
211
Single Conversion Mode
211
Continuous Conversion Mode
211
Timing Diagram
212
Analog Watchdog
212
Table 9-2 Analog Watchdog Channel Selection
212
Figure 9-5 Timing Diagram
212
Scanning Mode
213
Injection Channel Management
213
Discontinuous Mode
214
Figure 9-6 Injection Conversion Delay
214
Calibration
215
Data Aligned
215
Figure 9-7 Calibration Sequence Diagram
215
Programmable Channel Sampling Time
216
Externally Triggered Conversion
216
Table 9-3 Right-Align Data
216
Table 9-4 Left-Aligne Data
216
Table 9-5 External Trigger for Regular Channels of ADC1 and ADC2
217
Table 9-6 External Trigger for Regular Channels of ADC3 and ADC4
217
Table 9-7 External Trigger for Injection Channel of ADC1 and ADC2
217
DMA Requests
218
ADC Mode
218
Table 9-8 External Trigger for Injection Channel of ADC3 and ADC4
218
Independent Mode
219
Synchronous Regular Mode
219
Figure 9-8 Dual ADC Block Diagram
219
Synchronous Injection Mode
220
Figure 9-9 Schematic Diagram of Synchronous Regular Mode Conversion of 16 Channels
220
Fast Alternate Mode
221
Figure 9-10 Schematic Diagram of Synchronous Injection Mode Conversion of 4 Channels
221
Slow Alternate Mode
222
Figure 9-11 Schematic Diagram of Fast Alternate Mode Conversion for Continuous Conversion of 1 Channel
222
Rotation Trigger Mode
223
Figure 9-12 Schematic Diagram of Slow Alternate Mode Conversion for 1 Channel
223
Figure 9-13 Rotation Triggering: Injecting Channel Groups
223
Mixed Synchronous Regular Mode + Synchronous Injection Mode
224
Mixed Synchronous Regular Mode + Rotation Trigger Mode
224
Figure 9-14 Rotation Trigger: Inject Channel Group in Discontinuous Mode
224
Mixed Synchronous Injection Mode + Alternate Mode
225
Figure 9-15 Combination of Rotation Mode and Synchronous Regular Mode
225
Figure 9-16 Injection Trigger Occurs During Injection Transition
225
Temperature Sensor
226
Figure 9-17 Alternate Single-Channel Conversions Are Interrupted by Injection Sequences CH3 and CH4
226
Temperature Sensor Using Flow
227
ADC Interrupt
227
Figure 9-18 Temperature Sensor and VREFINT Diagram of the Channel
227
ADC Registers
228
ADC Register Overview
228
Table 9-9 ADC Interrupt
228
Table 9-10 ADC Register Overview
228
ADC Status Register (ADC_STS)
229
ADC Control Register 1 (ADC_CTRL1)
230
ADC Control Register 2 (ADC_CTRL2)
233
ADC Sampling Time Register 1 (ADC_SAMPT1)
235
ADC Sampling Time Register 2 (ADC_ SAMPT2)
235
ADC Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1
236
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
236
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
237
ADC Regular Sequence Register 1 (ADC_RSEQ1)
237
ADC Regular Sequence Register 2 (ADC_RSEQ2)
238
ADC Regular Sequence Register 3 (ADC_RSEQ3)
238
ADC Injection Sequence Register (ADC_JSEQ)
239
ADC Injection Data Register X (Adc_Jdatx) (X= 1
240
ADC Regulars Data Register (ADC_DAT)
240
ADC Differential Mode Selection Register (ADC_DIFSEL)
240
ADC Calibration Factor (ADC_CALFACT)
241
ADC Control Register 3 (ADC_CTRL3)
242
ADC Sampling Time Register 3 (ADC_SAMPT3)
243
Digital to Analog Conversion (DAC)
244
Introduction
244
Main Features
244
Table 10-1 DAC Pins
245
Figure 10-1 Block Diagram of a DAC Channel
245
DAC Function Description and Operation Description
246
DAC Enable
246
DAC Output Buffer
246
DAC Data Format
246
Figure 10-2 Data Format When DAC Independent Output
247
DAC Trigger
248
Table 10-2 DAC External Trigger
248
Figure 10-3 Data Format for DAC Sync Output
248
DAC Conversion
249
DAC Output Voltage
249
Figure 10-4 Time Diagram of Transitions with Trigger Disabled
249
DMA Requests
250
The Noise
250
Figure 10-5 LFSR Algorithm for DAC
250
Triangular Wave Generation
251
Figure 10-6 DAC Conversion with LFSR Waveform Generation (Enable Software Trigger)
251
Figure 10-7 Triangle Wave Generation of DAC
251
DAC Dual-Channel Conversion
252
Independent Trigger Without Waveform Generator
252
Independent Triggers Producing the same Noise
252
Figure 10-8 DAC Conversion with Trigonometry Generation (Enable Software Trigger)
252
Independent Triggers that Generate Different Noises
253
Independent Triggers that Generate the same Triangle Wave
253
Independent Trigger to Generate Different Triangle Waves
254
Simultaneous Software Startup
254
Synchronous Trigger Without Waveform Generator
255
Synchronous Triggers that Generate the same Noise
255
Synchronous Triggers that Generate Different Noises
255
Synchronous Trigger to Generate the same Triangle Wave
256
Synchronous Trigger to Generate Different Triangle Waves
256
DAC Register
257
DAC Registers Overview
257
DAC Control Register (DAC_CTRL)
257
Table 10-3 DAC Registers Overvie
257
DAC Software Trigger Register (DAC_SOTTR)
260
Bit Right Aligned Data Hold Register for DAC1 (DAC_DR12CH1)
260
Bit Left Aligned Data Hold Register for DAC1 (DAC_DL12CH1)
261
8-Bit Right-Aligned Data Hold Register for DAC1 (DAC_DR8CH1)
261
Bit Right Aligned Data Hold Register for DAC2 (DAC_DR12CH2)
262
Bit Left Aligned Data Hold Register for DAC2 (DAC_DL12CH2)
262
8-Bit Right-Aligned Data Hold Register for DAC2 (DAC_DR8CH2)
262
Bit Right Aligned Data Hold Register for Dual DAC (DAC_DR12DCH)
263
Bit Left Aligned Data Hold Register for Dual DAC (DAC_DL12DCH)
263
Bit Right Aligned Data Hold Register for Dual DAC (DAC_DR8DCH)
264
DAC1 Data Output Register (DAC_DATO1)
264
DAC2 Data Output Register (DAC_DATO2)
265
Advanced-Control Timers (TIM1 and TIM8)
266
TIM1 and TIM8 Introduction
266
Main Features of TIM1 and TIM8
266
TIM1 and TIM8 Function Description
267
Time-Base Unit
267
Figure 11-1 Block Diagram of TIM1 and TIM8
267
Counter Mode
268
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
268
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
269
Figure 11-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
271
Figure 11-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
272
Figure 11-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
272
Repetition Counter
273
Figure 11-8 Repeat Count Sequence Diagram in Down-Counting Mode
274
Figure 11-9 Repeat Count Sequence Diagram in Up-Counting Mode
275
Figure 11-10 Repeat Count Sequence Diagram in Center-Aligned Mode
275
Clock Selection
276
Figure 11-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
276
Figure 11-12 TI2 External Clock Connection Example
277
Figure 11-13 Control Circuit in External Clock Mode 1
278
Figure 11-14 External Trigger Input Block Diagram
278
Capture/Compare Channels
279
Figure 11-15 Control Circuit in External Clock Mode 2
279
Figure 11-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
280
Figure 11-17 Capture/Compare Channel 1 Main Circuit
281
Input Capture Mode
282
Figure 11-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
282
Figure 11-19 Output Part of Channelx (X= 4)
282
PWM Input Mode
283
Forced Output Mode
284
Figure 11-20 PWM Input Mode Timing
284
Output Compare Mode
285
PWM Mode
286
Figure 11-21 Output Compare Mode, Toggle on OC1
286
Figure 11-22 Center-Aligned PWM Waveform (AR=8)
287
Figure 11-23 Edge-Aligned PWM Waveform (APR=8)
288
One-Pulse Mode
289
Clearing the Ocxref Signal on an External Event
290
Complementary Outputs with Dead-Time Insertion
291
Figure 11-24 Clearing the Ocxref of Timx
291
Figure 11-25 Complementary Output with Dead-Time Insertion
292
Break Function
293
Figure 11-26 Output Behavior in Response to a Break
294
Debug Mode
295
Timx and External Trigger Synchronization
295
Figure 11-27 Control Circuit in Reset Mode
295
Figure 11-28 Control Circuit in Trigger Mode
296
Figure 11-29 Control Circuit in Gated Mode
297
Timer Synchronization
298
6-Step PWM Generation
298
Figure 11-30 Control Circuit in Trigger Mode + External Clock Mode2
298
Encoder Interface Mode
299
Figure 11-31 6-Step PWM Generation, COM Example (OSSR=1)
299
Table 11-1 Counting Direction Versus Encoder Signals
300
Figure 11-32 Example of Counter Operation in Encoder Interface Mode
300
Figure 11-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
301
Interfacing with Hall Sensor
302
Figure 11-34 Example of Hall Sensor Interface
303
Timx Register (X=1, 8)
304
Register Overview
304
Table 11-2 Register Map and Reset Value
304
Control Register 1 (Timx_Ctrl1)
305
Control Register 2 (Timx_Ctrl2)
308
Slave Mode Control Register (Timx_Smctrl)
309
Table 11-3 Timx Internal Trigger Connection
311
Dma/Interrupt Enable Registers (Timx_Dinten)
312
Status Registers (Timx_Sts)
313
Event Generation Registers (Timx_Evtgen)
315
Capture/Compare Mode Register 1 (Timx_Ccmod1)
316
Capture/Compare Mode Register 2 (Timx_Ccmod2)
320
Capture/Compare Enable Registers (Timx_Ccen)
321
Table 11-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
323
Counters (Timx_Cnt)
324
Prescaler (Timx_Psc)
324
Auto-Reload Register (Timx_Ar)
324
Repeat Count Registers (Timx_Repcnt)
325
Capture/Compare Register 1 (Timx_Ccdat1)
325
Capture/Compare Register 2 (Timx_Ccdat2)
326
Capture/Compare Register 3 (Timx_Ccdat3)
326
Capture/Compare Register 4 (Timx_Ccdat4)
327
Break and Dead-Time Registers (Timx_Bkdt)
327
DMA Control Register (Timx_Dctrl)
329
DMA Transfer Buffer Register (Timx_Daddr)
330
Capture/Compare Mode Registers 3(Timx_Ccmod3)
331
Capture/Compare Register 5 (Timx_Ccdat5)
331
Capture/Compare Register 6 (Timx_Ccdat6)
332
General-Purpose Timers (TIM2, TIM3, TIM4 and TIM5)
333
General-Purpose Timers Introduction
333
Main Features of General-Purpose Timers
333
General-Purpose Timers Description
334
Time-Base Unit
334
Figure 12-1 Block Diagram of Timx(X=2, 3 ,4 and 5
334
Counter Mode
335
Figure 12-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
335
Figure 12-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
336
Figure 12-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
337
Figure 12-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
338
Figure 12-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
339
Clock Selection
340
Figure 12-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
340
Figure 12-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
341
Figure 12-9 TI2 External Clock Connection Example
342
Figure 12-10 Control Circuit in External Clock Mode 1
343
Figure 12-11 External Trigger Input Block Diagram
343
Capture/Compare Channels
344
Figure 12-12 Control Circuit in External Clock Mode 2
344
Figure 12-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
345
Figure 12-14 Capture/Compare Channel 1 Main Circuit
346
Input Capture Mode
347
Figure 12-15 Output Part of Channelx (X = 1,2,3,4;Take Channel 4 as an Example
347
PWM Input Mode
348
Forced Output Mode
349
Output Compare Mode
349
Figure 12-16 PWM Input Mode Timing
349
PWM Mode
351
Figure 12-17 Output Compare Mode, Toggle on OC1
351
Figure 12-18 Center-Aligned PWM Waveform (AR=8)
352
Figure 12-19 Edge-Aligned PWM Waveform (APR=8)
353
One-Pulse Mode
354
Figure 12-20 Example of One-Pulse Mode
354
Clearing the Ocxref Signal on an External Event
355
Debug Mode
356
Timx and External Trigger Synchronization
356
Timer Synchronization
356
Figure 12-21 Control Circuit in Reset Mode
356
Figure 12-22 Block Diagram of Timer Interconnection
357
Figure 12-23 TIM2 Gated by OC1REF of TIM1
358
Figure 12-24 TIM2 Gated by Enable Signal of TIM1
359
Figure 12-25 Trigger TIM2 with an Update of TIM1
360
Encoder Interface Mode
361
Table 12-1 Counting Direction Versus Encoder Signals
361
Figure 12-26 Triggers Timers 1 and 2 Using the TI1 Input of TIM1
361
Figure 12-27 Example of Counter Operation in Encoder Interface Mode
362
Interfacing with Hall Sensor
363
Timx Register Description(X=2, 3 ,4 and 5)
363
Register Overview
363
Table 12-2 Register Map and Reset Value
363
Figure 12-28 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
363
Control Register 1 (Timx_Ctrl1)
365
Control Register 2 (Timx_Ctrl2)
367
Slave Mode Control Register (Timx_Smctrl)
368
Table 12-3 Timx Internal Trigger Connection
370
Dma/Interrupt Enable Registers (Timx_Dinten)
371
Status Registers (Timx_Sts)
372
Event Generation Registers (Timx_Evtgen)
373
Capture/Compare Mode Register 1 (Timx_Ccmod1)
374
Capture/Compare Mode Register 2 (Timx_Ccmod2)
377
Capture/Compare Enable Registers (Timx_Ccen)
379
Counters (Timx_Cnt)
380
Table 12-4 Output Control Bits of Standard Ocx Channel
380
Prescaler (Timx_Psc)
381
Auto-Reload Register (Timx_Ar)
381
Capture/Compare Register 1 (Timx_Ccdat1)
381
Capture/Compare Register 2 (Timx_Ccdat2)
382
Capture/Compare Register 3 (Timx_Ccdat3)
382
Capture/Compare Register 4 (Timx_Ccdat4)
383
DMA Control Register (Timx_Dctrl)
383
DMA Transfer Buffer Register (Timx_Daddr)
384
Basic Timers (TIM6 and TIM7)
386
Introduction
386
Main Features
386
Figure 13-1 Block Diagram of Timx(X = 6 and 7
386
Basic Timers Description
387
Time-Base Unit
387
Figure 13-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
387
Counter Mode
388
Figure 13-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
389
Figure 13-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
390
Clock Selection
391
Debug Mode
391
Timx Register Description(X = 6 and 7)
391
Figure 13-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
391
Register Overview
392
Control Register 1 (Timx_Ctrl1)
392
Table 13-1 Register Overview
392
Control Register 2 (Timx_Ctrl2)
393
Dma/Interrupt Enable Registers (Timx_Dinten)
394
Status Registers (Timx_Sts)
395
Event Generation Registers (Timx_Evtgen)
395
Counter (Timx_Cnt)
396
Prescaler (Timx_Psc)
396
Automatic Reload Register (Timx_Ar)
396
Real-Time Clock (RTC)
398
Description
398
Specification
398
Table 14-1 RTC Feature Support
398
RTC Function Description
399
RTC Block Diagram
399
Figure 14-1 RTC Block Diagram
399
Gpios of RTC
400
RTC Register Write Protection
400
RTC Clock and Prescaler
400
RTC Calendar
401
Calendar Initialization and Configuration
401
Calendar Reading
401
Calibration Clock Output
402
Programmable Alarms
403
Alarm Configuration
403
Alarm Output
403
Periodic Automatic Wakeup
403
Wakeup Timer Configuration
404
Timestamp Function
404
Daylight Saving Time Configuration
404
RTC Sub-Second Register Shift
405
RTC Digital Clock Precision Calibration
405
RTC Low Power Mode
406
RTC Registers
407
RTC Register Overview
407
Table 14-2 RTC Register Overview
407
RTC Calendar Time Register (RTC_TSH)
408
RTC Calendar Date Register (RTC_DATE)
408
RTC Control Register (RTC_CTRL)
409
RTC Initial Status Register (RTC_INITSTS)
411
RTC Prescaler Register (RTC_PRE)
413
RTC Wakeup Timer Register (RTC_WKUPT)
413
RTC Alarm a Register (RTC_ALARMA)
414
RTC Alarm B Register (RTC_ ALARMB)
415
RTC Write Protection Register (RTC_WRP)
416
RTC Sub-Second Register (RTC_SUBS)
416
RTC Shift Control Register (RTC_ SCTRL)
417
RTC Timestamp Time Register (RTC_TST)
417
RTC Timestamp Date Register (RTC_TSD)
418
RTC Timestamp Sub-Second Register (RTC_TSSS)
419
RTC Calibration Register (RTC_CALIB)
419
RTC Alarm a Sub-Second Register (RTC_ ALRMASS)
420
RTC Alarm B Sub-Second Register (RTC_ ALRMBSS)
421
RTC Option Register (RTC_ OPT)
421
CRC Calculation Unit
423
Introduction
423
Main Features
423
Crc32
423
Crc16
423
Function Description
424
Crc32
424
Crc16
424
Figure 15-1 CRC Calculation Unit Block Diagram
424
CRC Registers
425
CRC Register Overview
425
CRC32 Data Register (CRC_CRC32DAT)
425
CRC32 Independent Data Register (CRC_CRC32IDAT)
425
Table 15-1 CRC Register Overview
425
CRC32 Control Register (CRC_CRC32CTRL)
426
CRC16 Control Register (CRC_CRC16CTRL)
426
CRC16 Input Data Register (CRC_CRC16DAT)
427
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
427
LRC Result Register (CRC_LRC)
428
Independent Watchdog (IWDG)
429
Introduction
429
Main Features
429
Functional Description
430
Register Access Protection
430
Figure 16-1 Functional Block Diagram of the Independent Watchdog Module
430
Debug Mode
431
User Interface
431
Operate Flow
431
IWDG Configuration Flow
432
Table 16-1 IWDG Counting Maximum and Minimum Reset Time
432
IWDG Registers
433
IWDG Register Overview
433
IWDG Key Register (IWDG_KEY)
433
IWDG Pre-Scaler Register (IWDG_PREDIV)
433
Table 16-2 IWDG Register Overview
433
IWDG Reload Register (IWDG_RELV)
434
IWDG Status Register (IWDG_STS)
435
Window Watchdog (WWDG)
436
Introduction
436
Main Features
436
Function Description
436
Figure 17-1 Watchdog Block Diagram
436
Timing for Refresh Watchdog and Interrupt Generation
437
Figure 17-2 Refresh Window and Interrupt Timing of WWDG
437
Debug Mode
438
User Interface
438
WWDG Configuration Flow
438
Table 17-1 Maximum and Minimum Counting Time of WWDG
438
WWDG Registers
439
WWDG Register Overview
439
WWDG Control Register (WWDG_CTRL)
439
WWDG Config Register (WWDG_CFG)
439
Table 17-2 WWDG Register Overview
439
WWDG Status Register (WWDG_STS)
440
SDIO Interface(Sdio
441
Main Features of SDIO
441
SDIO Bus Topology
442
Figure 18-1 SDIO "No Response" and "No Data" Operations
443
Figure 18-2 SDIO (Multi) Data Block Read Operation
443
Figure 18-3 SDIO (Multiple) Data Block Write Operation
443
Figure 18-4 SDIO Continuous Read Operation
443
SDIO Function Description
444
SDIO Adapter
444
Figure 18-5 SDIO Continuous Write Operation
444
Figure 18-6 SDIO Block Diagram
444
Figure 18-7 SDIO Adapter
445
Table 18-1 MMC/SD/SD I/O Card Bus Pin Definition
446
Figure 18-8 Control Unit
447
Figure 18-9 SDIO Adapter Command Unit
448
Figure 18-10 Command Path State Machine (CPSM)
448
Table 18-2 Command Channel Status Flags
450
Figure 18-11 SDIO Command Transmission
450
Figure 18-12 Data Channel
451
Figure 18-13 Data Path State Machine (DPSM)
452
Table 18-3 Data Token Format
453
Table 18-4 Transmit FIFO Status Flags
454
Table 18-5 Receive FIFO Status Flags
454
SDIO AHB Interface
455
Card Function Description
456
Confirmation of Working Voltage Range
456
Card Reset
456
Card Identification Mode
457
Card Identification Process
457
Write Data Block
458
Read Data Block
459
Data Streaming Operation (Only for Multimedia Card)
459
Erase
461
Wide Bus Selection and De-Selection
461
Protection Management
461
Table 18-6 Lock/Unlock Data Structure
462
Card Status Register
465
Table 18-7 Card Status
465
Table 18-8 SD Status
468
Table 18-9 Speed Type Codes
470
Table 18-10 Mobility Performance Codes
470
Table 18-11 AU_SIZE Codes
470
Table 18-12 Maximum AU Size
471
Table 18-13 ERASE_SIZE Codes
471
Table 18-14 Erase Timeout Code
471
SD I/O Mode
472
Table 18-15 Erase Offset Codes
472
Commands and Responses
473
Application Related Commands and General Commands
473
Commands of Multimedia Card/Sd Card Module
474
Table 18-16 Write Commands for Block-Based Transfers
474
Table 18-17 Block-Based Write-Protect Commands
475
Table 18-18 Erase Command
475
Table 18-19 I/O Mode Command
475
Command Type
476
Table 18-20 Lock Command
476
Table 18-21 Application Related Commands
476
Command Format
477
Table 18-22 Command Format
477
Table 18-23 Short Response Format
477
Response Format
478
Table 18-24 Long Response Format
478
Table 18-25 R1 Response
478
Table 18-26 R2 Response
479
Table 18-27 R3 Response
479
Table 18-28 R4 Response
479
Table 18-29 R4B Response
480
Table 18-30 R5 Response
480
Table 18-31 R6 Response
480
Hardware Flow Control
481
SDIO Register
481
SDIO Register Overview
482
Table 18-32 SDIO Register Overview
482
SDIO Power Control Register (SDIO_PWRCTRL)
483
SDIO Clock Control Register (SDIO_CLKCTRL)
483
SDIO Command Argument Register (SDIO_CMDARG)
484
SDIO Command Register (SDIO_CMDCTRL)
485
SDIO Command Response Register(SDIO_CMDRESP)
486
SDIO Response 1
486
SDIO Data Timer Register (SDIO_DTIMER)
487
Table 18-33 Response Type and Sdio_Responsex Register
487
SDIO Data Length Register (SDIO_DATLEN)
488
SDIO Data Control Register (SDIO_DATCTRL)
488
SDIO Data Counter Register (SDIO_DATCOUNT)
490
SDIO Status Register (SDIO_STS)
490
SDIO Interrupt Clear Register (SDIO_INTCLR)
491
SDIO Interrupt Enable Register (SDIO_INTEN)
492
SDIO FIFO Counter Register (SDIO_FIFOCOUNT)
495
SDIO Data FIFO Register (SDIO_DATFIFO)
496
Universal Serial Bus Full-Speed Device Interface (Usb_Fs_Device)
497
Introduction
497
Main Features
497
Figure 19-1 USB Device Block Diagram
497
Clock Configuration
498
Functional Description
498
Access Packet Buffer Memory
498
Buffer Description Table
499
Figure 19-2 the User Applications on the Microcontrollers and the USB Modules Access Packet Buffer Memory
499
Double-Buffered Endpoints
500
Figure 19-3 the Relationship between the Buffer Description Table and the Endpoint Packet Buffer
500
Table 19-1 DATTOG and SW_BUF Definitions
501
Table 19-2 How to Use Double Buffering
501
USB Transfer
503
Figure 19-4 Double Buffered Bulk Endpoint Example
503
Figure 19-5 Control Transfer
507
USB Events and Interrupts
508
Table 19-3 How to Use Isochronous Double Buffering
508
Table 19-4 Resume Event Detection
509
Endpoint Initialization
510
USB Registers
510
USB Register Overview
511
Table 19-5 USB Register Overview
511
USB Endpoint N Register (Usb_Epn), N=[0
512
USB Control Register (USB_CTRL)
514
Table 19-6 Receive Status Code
514
Table 19-7 Send Status Code
514
USB Interrupt Status Register (USB_STS)
516
USB Frame Number Register (USB_FN)
519
USB Device Address Register (USB_ADDR)
519
USB Packet Buffer Description Table Address Register (USB_BUFTAB)
520
Buffer Description Table
520
Send Buffer Address Register N (Usb_Addrn_Tx)
521
Send Data Byte Number Register N (Usb_Cntn_Tx)
521
Receive Buffer Address Register N (Usb_Addrn_Rx)
521
Receive Data Byte Number Register N (Usb_Cntn_Rx)
522
Table 19-8 Endpoint Packet Receive Buffer Size Definition
522
Controller Area Network (CAN)
524
Introduction to CAN
524
Main Features of CAN
524
CAN Overall Introduction
525
CAN Module
525
CAN Working Mode
525
Figure 20-1 Topology of CAN Network
525
Send Mailbox
527
Receiving Filter
527
Receive FIFO
527
Figure 20-2 CAN Working Mode
527
Figure 20-3 Dual CAN Block Diagram
528
CAN Test Mode
529
Figure 20-4 Loopback Mode
529
Figure 20-5 Silent Mode
530
Figure 20-6 Loopback Silent Mode
530
CAN Debugging Mode
531
CAN Function Description
531
Send Processing
531
Time Triggered Communication Mode
532
Non-Automatic Retransmission Mode
532
Receiving Management
533
Figure 20-7 Send Mailbox Status
533
Figure 20-8 Receive FIFO Status
534
Identifier Filtering
535
Figure 20-9 Filter Bit Width Setting-Register Organization
536
Table 20-1 Examples of Filter Numbers
537
Message Storage
538
Figure 20-10 Examples of Filter Mechanisms
538
Bit Time Characteristic
539
Table 20-2 Send Mailbox Register List
539
Table 20-3 Receive Mailbox Register List
539
Figure 20-11 Bit Sequence
540
Figure 20-12 Various CAN Frames
541
CAN Interrupt
542
Figure 20-13 Event Flag and Interrupt Generation
542
Error Management
543
Bus-Off Recovery
543
CAN Configuration Flow
543
Figure 20-14 CAN Error State Diagram
543
CAN Register File
545
Register Description
545
CAN Register Address Overview
546
Table 20-4 CAN Register Overview
546
CAN Control and Status Register
550
CAN Mailbox Register
561
CAN Filter Register
566
Serial Peripheral Interface/Inter-IC Sound (SPI/ I 2 S)
570
Introduction
570
Main Features
570
SPI Features
570
I 2 S Features
570
SPI Function Description
571
General Description
571
Figure 21-1 SPI Block Diagram
571
Figure 21-2 Selective Management of Hardware/Software
572
Figure 21-3 Master and Slave Applications
573
SPI Work Mode
574
Figure 21-4 Data Clock Timing Diagram
574
Figure 21-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full Duplex Mode
575
Figure 21-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode
576
Figure 21-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode
576
(BIDIRMODE = 0 and RONLY = 1)
576
Figure 21-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in
578
Full Duplex Mode
578
Figure 21-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit-Only Mode
578
Status Flag
580
Figure 21-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted
580
Discontinuously
580
Disabling the SPI
581
SPI Communication Using DMA
582
Figure 21-11 Transmission Using DMA
582
CRC Calculation
583
Figure 21-12 Reception Using DMA
583
Error Flag
584
SPI Interrupt
584
Table 21-1 SPI Interrupt Request
584
I 2 S Function Description
585
Figure 21-13 I 2 S Block Diagram
585
Supported Audio Protocols
586
Figure 21-14 I 2 S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
587
Figure 21-15 I 2 S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
587
Figure 21-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
589
Figure 21-18 MSB Aligns 24-Bit Data, CLKPOL = 0
589
Figure 21-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
589
Figure 21-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
590
Figure 21-21 LSB Aligns 24-Bit Data, CLKPOL = 0
590
Figure 21-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
591
Clock Generator
592
Figure 21-23 PCM Standard Waveform (16 Bits)
592
Figure 21-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
592
Figure 21-25 I 2 S Clock Generator Structure
593
Figure 21-26 Audio Sampling Frequency Definition
593
I 2 S Transmission and Reception Sequence
594
Table 21-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency
594
Status Flag
596
Error Flag
597
I 2 S Interrupt
597
DMA Function
597
Table 21-3 I 2 S Interrupt Request
597
SPI and I S Register
598
SPI Register Overview
598
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
598
Table 21-4 SPI Register Overview
598
SPI Control Register 2 (SPI_CTRL2)
601
SPI Status Register (SPI_STS)
601
SPI Data Register (SPI_DAT)
603
SPI CRC Polynomial Register (SPI_CRCPOLY)
603
Mode)
603
SPI RX CRC Register (SPI_CRCRDAT)
603
SPI TX CRC Register(Spi_Crctdat
604
SPI_ I 2 S Configuration Register(Spi_I2Scfg
604
SPI_I S Prescaler Register (SPI_I2SPREDIV)
606
I 2 C Interface
607
Introduction
607
Main Features
607
Function Description
607
SDA and SCL Line Control
607
Software Communication Process
608
Figure 22-1 I 2 C Functional Block Diagram
609
Figure 22-2 I2C Bus Protocol
609
Figure 22-3 Slave Transmitter Transfer Sequence Diagram
612
Figure 22-4 Slave Receiver Transfer Sequence Diagram
613
Figure 22-5 Master Transmitter Transfer Sequence Diagram
615
Figure 22-6 Master Receiver Transfer Sequence Diagram
617
Error Conditions Description
618
DMA Application
619
Packet Error Check
620
Smbus
621
Table 22-1 Comparison between Smbus and I2C
621
Debug Mode
623
Interrupt Request
623
Table 22-2 I 2 C Interrupt Request
623
I2C Registers
624
I2C Register Overview
624
Table 22-3 I2C Register Overview
624
I2C Control Register 1 (I2C_CTRL1)
625
I2C Control Register 2 (I2C_CTRL2)
627
I2C Own Address Register 1 (I2C_OADDR1)
628
I2C Own Address Register 2 (I2C_OADDR2)
629
I2C Data Register (I2C_DAT)
629
I2C Status Register 1 (I2C_STS1)
629
I2C Status Register 2 (I2C_STS2)
633
I2C Clock Control Register (I2C_CLKCTRL)
634
I2C Rise Time Register (I2C_TMRISE)
635
Universal Synchronous Asynchronous Receiver Transmitter (USART)
636
Introduction
636
Main Features
636
Functional Block Diagram
637
Function Description
637
Figure 23-1 USART Block Diagram
637
USART Frame Format
638
Figure 23-2 Word Length = 8 Setting
638
Transmitter
639
Table 23-1 Stop Bit Configuration
639
Figure 23-3 Word Length = 9 Setting
639
Figure 23-4 Configuration Stop Bit
640
Receiver
641
Figure 23-5 TXC/TXDE Changes During Transmission
641
Figure 23-6 Start Bit Detection
642
Generation of Fractional Baud Rate
644
Table 23-2 Data Sampling for Noise Detection
644
Table 23-3 Error Calculation When Setting Baud Rate
645
Receiver's Tolerance Clock Deviation
646
Parity Control
646
Table 23-4 When Div_Decimal = 0. Tolerance of USART Receiver
646
Table 23-5 When Div_Decimal != 0. Tolerance of USART Receiver
646
Table 23-6 Frame Format
646
DMA Application
647
Figure 23-7 Transmission Using DMA
648
Hardware Flow Control
649
Figure 23-8 Reception Using DMA
649
Figure 23-9 Hardware Flow Control between Two USART
649
Figure 23-10 RTS Flow Control
650
Multiprocessor Communication
651
Figure 23-11 CTS Flow Controls
651
Figure 23-12 Mute Mode Using Idle Line Detection
652
Synchronous Mode
653
Figure 23-13 Mute Mode Detected Using Address Mark
653
Figure 23-14 USART Synchronous Transmission Example
654
Figure 23-15 USART Data Clock Timing Example (WL=0)
654
Single-Wire Half-Duplex Mode
655
Figure 23-16 USART Data Clock Timing Example (WL=1)
655
Figure 23-17 RX Data Sampling / Holding Time
655
Irda SIR ENDEC Mode
656
LIN Mode
657
Figure 23-18 Irdasirendec-Block Diagram
657
Figure 23-19 Irda Data Modulation (3/16)-Normal Mode
657
Figure 23-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
659
Smartcard Mode (ISO7816)
660
Figure 23-21 Break Detection and Framing Error Detection in LIN Mode
660
Figure 23-22 ISO7816-3 Asynchronous Protocol
661
Interrupt Request
662
Table 23-7 USART Interrupt Request
662
Figure 23-23 Use 1.5 Stop Bits to Detect Parity Errors
662
Mode Support
663
USART Registers
663
USART Register Overview
663
Table 23-9 USART Register Overview
663
USART Status Register (USART_STS)
664
USART Data Register (USART_DAT)
666
USART Baud Rate Register (USART_BRCF)
667
USART Control Register 1 Register (USART_CTRL1)
667
USART Control Register 2 Register (USART_CTRL2)
669
USART Control Register 3 Register (USART_CTRL3)
670
USART Guard Time and Prescaler Register (USART_GTP)
672
Quad Serial Peripheral Interface (QSPI)
674
Introduction
674
QSPI Main Features
674
Function Description
675
QSPI Command Sequence
675
Figure 24-1 QSPI Block Diagram
675
Operating Procedures
676
QSPI Indirect Mode
676
Figure 24-2 QSPI Command Sequence
676
QSPI Indirect Send Operation
677
QSPI Indirect Receive Operation
679
QSPI Register
681
QSPI Register Overview
681
Table 24-1 QSPI Register Overview
681
QSPI Control 0 Register (QSPI_CTRL0)
683
QSPI Control 1 Register (QSPI_CTRL1)
685
QSPI Enable Register (QSPI_EN)
685
QSPI Microwire Control Register (QSPI_MW_CTRL)
686
QSPI Slave Enable Register (QSPI_SLAVE_EN)
686
QSPI Baud Rate Select Register (QSPI_BAUD)
687
QSPI Transmit FIFO Threshold Level Register (QSPI_TXFT)
687
QSPI Receive FIFO Threshold Level Register (QSPI_RXFT)
688
QSPI Transmit FIFO Level Register (QSPI_TXFN)
688
QSPI Receive FIFO Level Register (QSPI_RXFN)
689
QSPI Status Register (QSPI_STS)
689
QSPI Interrupt Mask Register (QSPI_IMASK)
690
QSPI Interrupt Status Register (QSPI_ISTS)
691
QSPI Raw Interrupt Status Register (QSPI_RISTS)
692
QSPI Transmit FIFO Overflow Interrupt Clear Register (QSPI_TXFOI_CLR)
693
QSPI Receive FIFO Overflow Interrupt Clear Register (QSPI_RXFOI_CLR)
693
QSPI Receive FIFO Underflow Interrupt Clear Register (QSPI_RXFUI_CLR)
693
QSPI Multi-Master Interrupt Clear Register (QSPI_MMCI_CLR)
694
QSPI Interrupt Clear Register (QSPI_ICLR)
694
QSPI DMA Control Register (QSPI_DMA_CTRL)
695
QSPI DMA Transmit Data Level Register (QSPI_DMATDL_CTRL)
695
QSPI DMA Receive Data Level Register (QSPI_DMARDL_CTRL)
695
QSPI Data Register(Qspi_Datx
696
QSPI RX Sample Delay Register (QSPI_RS_DELAY)
696
QSPI Enhanced SPI Mode Control 0 Register(Qspi_Enh_Ctrl0
697
QSPI DDR Transmit Drive Edge Register (QSPI_DDR_TXDE)
698
QSPI XIP Mode Bits Register (QSPI_XIP_MODE)
698
QSPI XIP INCR Transfer Opcode Register (QSPI_XIP_INCR_TOC)
699
QSPI XIP WRAP Transfer Opcode Register (QSPI_XIP_WRAP_TOC)
699
QSPI XIP Control Register (QSPI_XIP_CTRL)
700
QSPI XIP Slave Enable Register (QSPI_XIP_SLAVE_EN)
701
QSPI XIP Receive FIFO Overflow Interrupt Clear Register (QSPI_XIP_RXFOI_CLR)
702
QSPI XIP Time out for Continuous Transfers Register(Qspi_Xip_Tout
702
Ethernet (ETH)
704
Introduction
704
Main Features
704
Function Block Diagram
706
Function Description
706
IEEE 802.3 Ethernet Frame Format
706
Figure 25-1 Ethernet Module Block Diagram
706
Pin Configuration (Alternate) Method
707
Table 25-1 ETH Module Pin Configuration (Alternate)
707
Figure 25-2 MAC Frame Format and Frame Structure
707
SMI Interface
708
Figure 25-3 SMI Interface Signal Line
708
MII Interface
709
Table 25-2 SMI Clock Configuration Range
709
Figure 25-4 MII Interface Signal Line
710
RMII Interface
711
Table 25-3 Transmit Interface Signal Code
711
Table 25-4 Receive Interface Signal Code
711
Figure 25-5 MII Clock Source
711
MAC Function Description
712
Figure 25-6 RMII Interface Signal Line
712
Figure 25-7 RMII Clock Source
712
Table 25-5 Destination Address Filter Result List
718
Table 25-6 Source Address Filter Result List
719
Power Management (PMT)
721
Table 25-7 Remote Wakeup Frame Filter Register Overview
722
Ethernet DMA Function Description
724
Figure 25-8 Two Structures of Descriptor
725
Table 25-8 Transmit Descriptor Overview
727
Table 25-9 Receive Descriptor Overview
734
Precision Time Protocol (PTP)
740
Figure 25-9 System Time Precision Calibration
741
Typical Ethernet Configuration Flow Example
743
Ethernet Interrupt
744
ETH Register
744
ETH Register Overview
745
Table 25-10 ETH Register Overview
745
ETH MAC Configuration Register (ETH_MACCFG)
748
ETH MAC Frame Filter Register (ETH_MACFFLT)
750
ETH MAC HASH List High Register (ETH_MACHASHHI)
752
ETH MAC HASH List Low Register (ETH_MACHASHLO)
752
ETH MAC MII Address Register (ETH_MACMIIADDR)
753
ETH MAC MII Data Register (ETH_MACMIIDAT)
754
ETH MAC Flow Control Register (ETH_MACFLWCTRL)
754
ETH MAC VLAN Tag Register (ETH_MACVLANTAG)
756
ETH MAC Remote Wakeup Frame Filter Register (ETH_MACRMTWUFRMFLT)
756
ETH MAC PMT Control and Status Register (ETH_MACPMTCTRLSTS)
757
ETH MAC Interrupt Status Register (ETH_MACINTSTS)
758
ETH MAC Interrupt Mask Register (ETH_MACINTMSK)
759
ETH MAC Address 0 High Register (ETH_MACADDR0HI)
759
ETH MAC Address 0 Low Register (ETH_MACADDR0LO)
760
ETH MAC Address 1 High Register (ETH_MACADDR1HI)
760
ETH MAC Address 1 Low Register (ETH_MACADDR1LO)
761
ETH MAC Address 2 High Register (ETH_MACADDR2HI)
761
ETH MAC Address 2 Low Register (ETH_MACADDR2LO)
762
ETH MAC Address 3 High Register (ETH_MACADDR3HI)
762
ETH MAC Address 3 Low Register (ETH_MACADDR3LO)
763
ETH MMC Control Register (ETH_MMCCTRL)
764
ETH MMC Receive Interrupt Status Register (ETH_MMCRXINT)
764
ETH MMC Transmit Interrupt Status Register (ETH_MMCTXINT)
765
ETH MMC Receive Interrupt Mask Register (ETH_MMCRXINTMSK)
766
ETH MMC Transmit Interrupt Mask Register (ETH_MMCTXINTMSK)
767
ETH MMC Transmitted "Good" Frame Counter Register after 1 Collision (ETH_MMCTXGFASCCNT)
767
ETH MMC Transmitted "Good" Frame Counter Register after more than 1 Collision
768
(Eth_Mmctxgfamsccnt)
768
ETH MMC Transmitted "Good" Frame Counter Register (ETH_MMCTXGFCNT)
768
ETH MMC CRC Error Received Frame Counter Register (ETH_MMCRXFCECNT)
769
ETH MMC Alignment Error Received Frame Counter Register (ETH_MMCRXFAECNT)
769
ETH MMC Receive "Good" Unicast Frame Counter Register (ETH_MMCRXGUFCNT)
769
ETH PTP Timestamp Control Register (ETH_PTPTSCTRL)
770
ETH PTP Subsecond Increment Register (ETH_PTPSSINC)
771
ETH PTP Timestamp High Register (ETH_PTPSEC)
771
ETH PTP Timestamp Low Register (ETH_PTPNS)
772
ETH PTP Timestamp High Update Register (ETH_PTPSECUP)
772
ETH PTP Timestamp Low Update Register (ETH_PTPNSUP)
773
ETH PTP Timestamp Addend Register (ETH_PTPTSADD)
773
ETH PTP Target Time High Register (ETH_PTPTTSEC)
774
ETH PTP Target Time Low Register (ETH_PTPTTNS)
774
ETH DMA Bus Mode Register (ETH_DMABUSMOD)
775
ETH DMA Transmit Query Request Register (ETH_DMATXPD)
777
ETH DMA Receive Query Request Register (ETH_DMARXPD)
777
ETH DMA Receive Descriptor List Address Register (ETH_DMARXDLADDR)
778
ETH DMA Transmit Descriptor List Address Register (ETH_DMATXDLADDR)
778
ETH DMA Status Register (ETH_DMASTS)
779
ETH DMA Operation Mode Register (ETH_DMAOPMOD)
783
ETH DMA Interrupt Enable Register (ETH_DMAINTEN)
785
ETH DMA Missed Frames and Buffer Overflow Counter Register (ETH_DMAMFBOCNT)
787
ETH DMA Current Transmit Descriptor Address Register (ETH_DMACHTXDESC)
788
ETH DMA Current Receive Descriptor Address Register (ETH_DMACHRXDESC)
788
ETH DMA Current Transmit Buffer Address Register (ETH_DMACHTXBADDR)
789
ETH DMA Current Receive Buffer Address Register (ETH_DMACHRXBADDR)
789
Comparator (COMP)
790
COMP System Connection Block Diagram
790
Figure 26-1 Comparator1 and Comparator2 Connection Diagram
790
Figure 26-2 Comparator3 and Comparator4 Connection Diagram
791
Figure 26-3 Comparator5,Comparator6,Comparator7 Connection Diagram
792
Main Features
793
COMP Configuration Process
793
COMP Working Mode
794
Window Mode
794
Independent Comparator
794
Comparator Interconnection
794
Interrupt
795
COMP Register
796
COMP Register Overview
796
Table 26-1 COMP Register Overview
796
COMP Control Register (Compx_Ctrl)
798
COMP Window Mode Register (COMP_WINMODE)
799
COMP Lock Register (COMP_LOCK)
800
COMP Interrupt Enable Register (COMP_INTEN)
800
COMP Interrupt Status Register (COMP_INTSTS)
801
COMP Filter Register (Compx_Filc)
801
COMP Filter Frequency Division Register (Compx_Filp)
802
COMP Reference Voltage Register (COMP_VREFSCL)
802
Operational Amplifier (OPAMP)
804
Main Features
804
OPAMP Function Description
804
Figure 27-1 Block Diagram of OPAMP1 and OPAMP2 Connection Diagram
805
Internal Connection between OPAMP and COMP
806
Figure 27-2 Block Diagram of OPAMP3 and OPAMP4 Connection Diagram
806
Figure 27-3 Simulation Module Linkage Relationship 1
807
Figure 27-4 Simulation Module Linkage Relationship 2
808
OPAMP Working Mode
809
OPAMP Independent Op Amp Mode
809
OPAMP Follow Mode
809
Figure 27-5 OPAMP Standalone Operational Amplifier Mode
809
OPAMP Internal Gain (PGA) Mode
810
Figure 27-6 Follow Mode
810
OPAMP with Filter Internal Gain Mode
811
Figure 27-7 Internal Gain Mode
811
Figure 27-8 Internal Gain Mode with Filter
811
OPAMP Calibration
812
OPAMP Independent Write Protection
812
OPAMP TIMER Controls the Switching Mode
812
OPAMP Register
812
OPAMP Register Overview
812
Table 27-1 OPAMP Register Overview
812
OPAMP Control Status Register (Opampx_Cs)
813
OPAMP Lock Register (OPAMP_LOCK)
815
DVP Interface (DVP)
816
Introduction
816
Hardware Interface
816
Pin Multiplexing Mode
816
Table 28-1 DVP Pin Multiplexing
816
Interface Timing
817
Operating Instructions
817
General Operation Process
817
Figure 28-1 DVP Interface Timing Example
817
DMA Application
818
Image Size
818
Image Area
818
Image Scaling
818
Soft Reset
819
Interrupts
819
Read FIFO Data
819
Notes
819
DVP Register
820
DVP Register Overview
820
DVP Control Register(Dvp_Ctrl
820
Table 28-2 DVP Register Overview
820
DVP Status Register(Dvp_Sts
822
DVP Interrupt Status Register(Dvp_Intsts
823
DVP Interrupt Enable Register
824
DVP Interrupt Trigger Status Register(Dvp_Mintsts
825
DVP Image Start Register(Dvp_Wst
827
DVP Image Size Register(Dvp_Wsize
827
DVP FIFO Register(Dvp_Fifo
827
Debug Support (DBG)
829
Overview
829
Figure 29-1 N32G45X Level and Cortex
829
TM -M4F Level Debugging Block Diagram
829
JTAG/SWD Function
830
Switch JTAG/SWD Interface
830
Pin Allocation
830
MCU Debugging Function
831
Low Power Mode Support
831
Peripheral Debugging Support
831
Table 29-1 Debug Port Pin
831
DBG Registers
832
DBG Register Overview
832
ID Register (DBG_ID)
832
Table 29-2 DBG Register Overview
832
Debug Control Register (DBG_CTRL)
833
Unique Device Serial Number (UID)
836
Introduction
836
UID Register
836
UCID Register
836
Version History
837
Notice
838
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