Nations N32G032 Series Manuals

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Nations N32G032 Series User Manual

Nations N32G032 Series User Manual (620 pages)

32-bit ARM Cortex-M0

Brand: Nations | Category: Microcontrollers | Size: 11 MB

Table of Contents

Table of Contents
2
Abbreviations in the Text
30
List of Abbreviations for Registers
30
Available Peripherals
30
Memory and Bus Architecture
31
System Architecture
31
Bus Architecture
31
Figure 2-1 Bus Architecture
32
Bus Address Mapping
33
Table 2-1 List of Peripheral Register Addresses
34
Figure 2-2 Bus Address Map
34
Boot Management
36
Memory System
37
FLASH Specification
37
Table 2-2 List of Boot Mode
37
Table 2-3 Flash Bus Address List
38
Option Byte
41
Table 2-4 Option Byte List
42
Write Protect
43
Table 2-5 Read Protection Configuration List
43
Table 2-6 Flash Read-Write-Erase
45
Sram
49
FLASH Register Description
50
Table 2-7 FLASH Register Overview
50
Power Control (PWR)
57
General Description
57
Power Supply
57
Power Supply Supervisor
58
Figure 3-1 Power Supply Block Diagram
58
Figure 3-2 Power on Reset/Power down Reset Waveform
59
Programmable Voltage Detector (PVD)
59
Power Modes
60
Table 3-1 Power Modes
60
Figure 3-3 PVD Threshold Diagram
60
Table 3-2 Peripheral Running Status
61
LPRUN Mode
62
SLEEP Mode
63
Enter SLEEP Mode
63
Exit SLEEP Mode
63
STOP Mode
63
PD Mode
64
Debug Support
65
Low Power Mode Debug Support
65
Peripheral Debug Support
65
PWR Registers
65
PWR Register Overview
65
Table 3-3 PWR Register Overview
65
Power Control Register (PWR_CTRL)
66
Power Control Status Register (PWR_CTRLSTS)
67
Power Control Register 2 (PWR_CTRL2)
69
Power Control Register 3 (PWR_CTRL3)
69
Power Control Register 4 (PWR_CTRL4)
69
Power Control Register 5 (PWR_CTRL5)
70
Power Control Register 6 (PWR_CTRL6)
71
Debug Control Register (DBG_CTRL)
71
Reset and Clock Control (RCC)
74
Reset Control Unit
74
Power Reset
74
System Reset
74
Software Reset
75
Low-Power Management Reset
75
Figure 4-1 System Reset Generation
75
Clock Control Unit
76
Clock Tree Diagram
78
Figure 4-2 Clock Tree
78
HSE Clock
79
Figure 4-3 HSE Clock Source
79
External Crystal/Ceramic Resonator (HSE Crystal)
79
HSI Clock
80
PLL Clock
80
LSE Clock
81
LSI Clock
81
Figure 4-4 PLL Clock Configuration
81
LSI Calibration
82
System Clock (SYSCLK) Selection
82
Clock Security System (CLKSS)
82
RTC Clock
83
Watchdog Clock
83
LPUART Clock
83
LPTIME Clock
83
Clock Output(MCO)
83
RCC Registers
84
RCC Register Overview
84
Table 4-1 RCC Register Overview
84
Clock Control Register (RCC_CTRL)
85
Clock Configuration Register (RCC_CFG)
87
Clock Interrupt Register (RCC_CLKINT)
89
APB2 Peripheral Reset Register (RCC_APB2PRST)
92
APB1 Peripheral Reset Register (RCC_APB1PRST)
94
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
96
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
97
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
99
Low Speed Clock Control Register (RCC_LSCTRL)
101
Control/Status Register (RCC_CTRLSTS)
102
AHB Peripheral Reset Register (RCC_AHBPRST)
104
Clock Configuration Register 2(RCC_CFG2)
105
EMC Control Register 3 (RCC_EMCCTRL)
107
GPIO and AFIO
111
Summary
111
Function Description
112
I/O Mode Configuration
112
Table 5-1 I/O Port Configuration Table
112
Figure 5-1 Basic Structure of I/O Ports
112
Table 5-2 I/O List of Functional Features of the Pin
113
Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode
114
Figure 5-3 Output Mode
115
Figure 5-4 Alternate Function Mode
116
Figure 5-5 Analog Function Mode with High Impedance
116
Status after Reset
117
Individual Bit Setting and Bit Clearing
117
External Interrupt /Wakeup Line
117
Alternate Function
117
Table 5-3 I/O List of Functional Features of the Pin
118
Table 5-4 TIM1 Alternate Function I/O Remapping
118
Table 5-5 TIM8 Alternate Function I/O Remapping
119
Table 5-6 TIM3 Alternate Function I/O Remapping
120
Table 5-7 TIM4 Alternate Function I/O Remapping
120
Table 5-8 LPTIM Alternate Function I/O Remapping
121
Table 5-9 CAN Alternate Function I/O Remapping
121
Table 5-10 USART1 Alternate Function I/O Remapping
122
Table 5-11 USART2 Alternate Function I/O Remapping
122
Table 5-12 UART5 Alternate Function I/O Remapping
123
Table 5-13 UART6 Alternate Function I/O Remapping
123
Table 5-14 LPUART1 Alternate Function I/O Remapping
123
Table 5-15 LPUART2 Alternate Function I/O Remapping
124
Table 5-16 I2C1 Alternate Function I/O Remapping
124
Table 5-17 I2C2 Alternate Function I/O Remapping
125
Table 5-18 SPI1/I2S1 Alternate Function I/O Remapping
126
Table 5-19 SPI2 Alternate Function I/O Remapping
126
Table 5-20 SPI3 Alternate Function I/O Remapping
127
Table 5-21 COMP1 Alternate Function I/O Remapping
127
Table 5-22 COMP2 Alternate Function I/O Remapping
127
Table 5-23 COMP3 Alternate Function I/O Remapping
127
Table 5-24 BEEPER1 Alternate Function I/O Remapping
128
Table 5-25 BEEPER2 Alternate Function I/O Remapping
128
Table 5-26 EVENTOUT Alternate Function I/O Remapping
128
Table 5-27 RTC Alternate Function I/O Remapping
129
Table 5-28 PVD Alternate Function I/O Remapping
129
Table 5-29 RCC Alternate Function I/O Remapping
129
Table 5-30 OSC_IN/OSC_OUT Alternate Function I/O Remapping
129
Table 5-31 OSC32 Alternate Function Remapping
129
Table 5-32 OSC Alternate Function Remapping
130
Table 5-33 ADC External Trigger Injection Conversion Alternate Function Remapping
130
Table 5-34 ADC External Trigger Regular Conversion Alternate Function Remapping
130
I/O Configuration of Peripherals
131
Table 5-35 TIM4_CH2 Alternate Function Remapping
131
Table 5-36 IO Signal Dual Voltage Levels Configuration
131
Table 5-37 ADC
131
Table 5-38 PVD
131
Table 5-39 TIM1/TIM8
131
Table 5-40 TIM3 and LPTIM
131
Table 5-41 CAN
132
Table 5-42 USART
132
Table 5-43 LPUART
132
Table 5-44 I2C
132
Table 5-45 SPI
132
GPIO Locking Mechanism
133
Table 5-46 COMP
133
Table 5-47 BEEPER
133
Table 5-48 Other
133
GPIO Registers
134
GPIO Register Overview
134
Table 5-49 GPIO Register Overview
134
GPIO Port Mode Description Register (Gpiox_Pmode)
135
GPIO Port Type Definition (Gpiox_Potype)
136
GPIO Slew Rate Configuration Register (Gpiox_Sr)
137
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupd)
137
GPIO Port Input Data Register (Gpiox_Pid)
138
GPIO Port Output Data Register (Gpiox_Pod)
138
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)
139
GPIO Port Configuration Lock Register (Gpiox_ PLOCK)
140
GPIO Alternate Function Low Register (Gpiox_Afl)
141
GPIO Alternate Function High Register (Gpiox_Afh)
141
GPIO Port Bit Clear Register (Gpiox_Pbc)
142
GPIO Driver Strength Configuration Register (Gpiox_ DS)
143
AFIO Registers
143
AFIO Register Overview
143
AFIO Configuration Register (AFIO_CFG)
144
Table 5-50 AFIO Register Overview
144
AFIO External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1)
145
AFIO External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2)
146
AFIO External Interrupt Configuration Register 3 (AFIO_EXTI_CFG3)
147
AFIO External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4)
148
Interrupts and Events
149
Nested Vectored Interrupt Controller
149
Systick Calibration Value Register
149
Interrupt and Exception Vectors
149
Table 6-1 Vector Table
149
External Interrupt/Event Controller (EXTI)
151
Introduction
151
Main Features
151
Functional Description
152
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram
152
EXTI Line Mapping
153
Figure 6-2 External Interrupt Generic I/O Mapping
153
EXTI Registers
155
EXTI Register Overview
155
Interrupt Mask Register(EXTI_IMASK)
155
Table 6-2 EXTI Register Overview
155
Event Mask Register(EXTI_EMASK)
156
Rising Edge Trigger Selection Register(EXTI_RT_CFG)
156
Falling Edge Trigger Selection Register(EXTI_FT_CFG)
157
Software Interrupt Enable Register(EXTI_SWIE)
157
Interrupt Request Pending Register(EXTI_PEND)
158
RTC Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
158
DMA Controller
159
Introduction
159
Main Features
159
Block Diagram
160
Function Description
160
DMA Operation
160
Figure 7-1 DMA Block Diagram
160
Channel Priority and Arbitration
161
DMA Channels and Number of Transfers
161
Programmable Data Bit Width, Alignment and Endians
161
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
162
Peripheral/Memory Address Incrementation
163
Channel Configuration Procedure
163
Flow Control
164
Table 7-2 Flow Control Table
164
Circular Mode
165
Error Management
165
Interrupt
165
DMA Request Mapping
166
Table 7-3 DMA Interrupt Request
166
Table 7-4 DMA Request Mapping
166
DMA Registers
167
DMA Register Overview
167
Table 7-5 DMA Register Overview
167
DMA Interrupt Status Register (DMA_INTSTS)
168
DMA Interrupt Flag Clear Register (DMA_INTCLR)
169
DMA Channel X Configuration Register (Dma_Chcfgx)
170
DMA Channel X Transfer Number Register (Dma_Txnumx)
171
DMA Channel X Peripheral Address Register (Dma_Paddrx)
172
DMA Channel X Memory Address Register (Dma_Maddrx)
172
DMA Channel X Channel Request Select Register (Dma_Chselx)
173
CRC Calculation Unit
174
CRC Introduction
174
CRC Main Features
174
CRC32 Module
174
CRC16 Module
174
CRC Function Description
175
Crc32
175
Crc16
175
Figure 8-1 CRC Calculation Unit Block Diagram
175
CRC Registers
176
CRC Register Overview
176
CRC32 Data Register (CRC_CRC32DAT)
176
CRC32 Independent Data Register (CRC_CRC32IDAT)
176
Table 8-1 CRC Register Overview
176
CRC32 Control Register (CRC_CRC32CTRL)
177
CRC16 Control Register (CRC_CRC16CTRL)
177
CRC16 Input Data Register (CRC_CRC16DAT)
178
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
178
LRC Result Register (CRC_LRC)
179
Advanced-Control Timers (TIM1 and TIM8)
180
TIM1 and TIM8 Introduction
180
Main Features of TIM1 and TIM8
180
TIM1 and TIM8 Function Description
181
Time-Base Unit
181
Figure 9-1 Block Diagram of TIM1 and TIM8
181
Prescaler Description
182
Counter Mode
182
Figure 9-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
182
Up-Counting Mode
182
Figure 9-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
184
Down-Counting Mode
186
Figure 9-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
186
Center-Aligned Mode
186
Figure 9-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
187
Figure 9-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
188
Counter Underflow
188
Repetition Counter
188
Figure 9-8 Repeat Count Sequence Diagram in Down-Counting Mode
189
Figure 9-9 Repeat Count Sequence Diagram in Up-Counting Mode
190
Figure 9-10 Repeat Count Sequence Diagram in Center-Aligned Mode
190
Clock Selection
191
Figure 9-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
191
Figure 9-12 TI2 External Clock Connection Example
192
Figure 9-13 Control Circuit in External Clock Mode 1
193
Figure 9-14 External Trigger Input Block Diagram
193
Capture/Compare Channels
194
Figure 9-15 Control Circuit in External Clock Mode 2
194
Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
195
Figure 9-17 Capture/Compare Channel 1 Main Circuit
196
Figure 9-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
196
Input Capture Mode
197
Figure 9-19 Output Part of Channelx (X= 4)
197
PWM Input Mode
198
Forced Output Mode
199
Figure 9-20 PWM Input Mode Timing
199
Output Compare Mode
200
PWM Mode
201
PWM Center-Aligned Mode
201
Figure 9-21 Output Compare Mode, Toggle on OC1
201
Figure 9-22 Center-Aligned PWM Waveform (AR=8)
202
Figure 9-23 Edge-Aligned PWM Waveform (APR=8)
203
One-Pulse Mode
204
Figure 9-24 Example of One-Pulse Mode
204
Clearing the Ocxref Signal on an External Event
205
Complementary Outputs with Dead-Time Insertion
206
Figure 9-25 Clearing the Ocxref of Timx
206
Figure 9-26 Complementary Output with Dead-Time Insertion
207
Break Function
208
Debug Mode
210
Timx and External Trigger Synchronization
210
Slave Mode: Reset Mode
210
Figure 9-27 Output Behavior in Response to a Break
210
Slave Mode: Trigger Mode
211
Figure 9-28 Control Circuit in Reset Mode
211
Slave Mode: Gated Mode
212
Figure 9-29 Control Circuit in Trigger Mode
212
Figure 9-30 Control Circuit in Gated Mode
213
Timer Synchronization
214
6-Step PWM Generation
214
Figure 9-31 Control Circuit in Trigger Mode + External Clock Mode2
214
Encoder Interface Mode
215
Figure 9-32 6-Step PWM Generation, COM Example (OSSR=1)
215
Table 9-1 Counting Direction Versus Encoder Signals
216
Figure 9-33 Example of Counter Operation in Encoder Interface Mode
216
Figure 9-34 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
217
Interfacing with Hall Sensor
218
Advanced-Control
219
Figure 9-35 Example of Hall Sensor Interface
219
Timx Register Description(X=1, 8)
220
Register Overview
220
Table 9-2 Register Overview
220
Control Register 1 (Timx_Ctrl1)
221
Control Register 2 (Timx_Ctrl2)
223
Slave Mode Control Register (Timx_Smctrl)
225
Table 9-3 Timx Internal Trigger Connection
227
Dma/Interrupt Enable Registers (Timx_Dinten)
228
Status Registers (Timx_Sts)
229
Event Generation Registers (Timx_Evtgen)
231
Capture/Compare Mode Register 1 (Timx_Ccmod1)
232
Capture/Compare Mode Register 2 (Timx_Ccmod2)
236
Capture/Compare Enable Registers (Timx_Ccen)
237
Table 9-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
239
Counters (Timx_Cnt)
240
Prescaler (Timx_Psc)
240
Auto-Reload Register (Timx_Ar)
241
Repeat Count Registers (Timx_Repcnt)
241
Capture/Compare Register 1 (Timx_Ccdat1)
242
Capture/Compare Register 2 (Timx_Ccdat2)
242
Capture/Compare Register 3 (Timx_Ccdat3)
243
Capture/Compare Register 4 (Timx_Ccdat4)
243
Break and Dead-Time Registers (Timx_Bkdt)
244
DMA Control Register (Timx_Dctrl)
246
DMA Transfer Buffer Register (Timx_Daddr)
246
Capture/Compare Mode Registers 3(Timx_Ccmod3)
247
Capture/Compare Register 5 (Timx_Ccdat5)
248
Capture/Compare Register 6 (Timx_Ccdat6)
248
General-Purpose Timers (TIM3 and TIM4)
249
General-Purpose Timers Introduction
249
Main Features of General-Purpose Timers
249
General-Purpose Timers Description
250
Time-Base Unit
250
Figure 10-1 Block Diagram of Timx（X=3 and 4
250
Counter Mode
251
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
251
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
252
Figure 9-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
253
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
253
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
254
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
255
Clock Selection
256
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
256
Figure 10-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
257
Figure 10-9 TI2 External Clock Connection Example
258
Figure 10-10 Control Circuit in External Clock Mode 1
259
Figure 10-11 External Trigger Input Block Diagram
259
Capture/Compare Channels
260
Figure 10-12 Control Circuit in External Clock Mode 2
260
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
261
Figure 10-14 Capture/Compare Channel 1 Main Circuit
262
Input Capture Mode
263
Figure 10-15 Output Part of Channelx （X = 1,2,3,4;Take Channel 4 as an Example
263
PWM Input Mode
264
Forced Output Mode
265
Output Compare Mode
265
Figure 10-16 PWM Input Mode Timing
265
PWM Mode
267
Figure 10-17 Output Compare Mode, Toggle on OC1
267
Figure 10-18 Center-Aligned PWM Waveform (AR=8)
268
Figure 10-19 Edge-Aligned PWM Waveform (APR=8)
269
One-Pulse Mode
270
Figure 10-20 Example of One-Pulse Mode
270
Clearing the Ocxref Signal on an External Event
271
Debug Mode
272
Timx and External Trigger Synchronization
272
Timer Synchronization
272
Figure 10-21 Control Circuit in Reset Mode
272
Figure 10-22 Block Diagram of Timer Interconnection
273
Figure 10-23 TIM3 Gated by OC1REF of TIM1
274
Figure 10-24 TIM3 Gated by Enable Signal of TIM1
275
Figure 10-25 Trigger TIM3 with an Update of TIM1
276
Encoder Interface Mode
277
Table 10-1 Counting Direction Versus Encoder Signals
277
Figure 10-26 Triggers Timers 1 and 3 Using the TI1 Input of TIM1
277
Figure 10-27 Example of Counter Operation in Encoder Interface Mode
278
Interfacing with Hall Sensor
279
Timx Register Description(X=3 and 4)
279
Register Overview
279
Table 10-2 Register Overview
279
Control Register 1 (Timx_Ctrl1)
281
Control Register 2 (Timx_Ctrl2)
283
Slave Mode Control Register (Timx_Smctrl)
284
Dma/Interrupt Enable Registers (Timx_Dinten)
286
Table 10-3 Timx Internal Trigger Connection
286
Status Registers (Timx_Sts)
287
Event Generation Registers (Timx_Evtgen)
289
Capture/Compare Mode Register 1 (Timx_Ccmod1)
290
Capture/Compare Mode Register 2 (Timx_Ccmod2)
293
Capture/Compare Enable Registers (Timx_Ccen)
295
Counters (Timx_Cnt)
296
Table 10-4 Output Control Bits of Standard Ocx Channel
296
Prescaler (Timx_Psc)
297
Auto-Reload Register (Timx_Ar)
297
Capture/Compare Register 1 (Timx_Ccdat1)
297
Capture/Compare Register 2 (Timx_Ccdat2)
298
Capture/Compare Register 3 (Timx_Ccdat3)
298
Capture/Compare Register 4 (Timx_Ccdat4)
299
DMA Control Register (Timx_Dctrl)
299
DMA Transfer Buffer Register (Timx_Daddr)
300
Basic Timers (TIM6)
302
Basic Timers Introduction
302
Main Features of Basic Timers
302
Basic Timers Description
302
Time-Base Unit
302
Figure 11-1 Block Diagram of Timx（X = 6
302
Counter Mode
303
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
303
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
304
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
305
Clock Selection
306
Debug Mode
306
Timx Register Description(X=6)
306
Figure 11-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
306
Register Overview
307
Control Register 1 (Timx_Ctrl1)
307
Table 11-1 Register Overview
307
Dma/Interrupt Enable Registers (Timx_Dinten)
308
Status Registers (Timx_Sts)
309
Event Generation Registers (Timx_Evtgen)
309
Counters (Timx_Cnt)
310
Prescaler (Timx_Psc)
310
Automatic Reload Register (Timx_Ar)
311
Low Power Timer (LPTIM)
312
Introduction
312
Main Features
312
Function Description
313
Block Diagram
313
LPTIM Reset and Clock
313
Figure 12-1 LPTIM Diagram
313
Glitch Filter
314
Figure 12-2 Glitch Filter Timing Diagram
314
Prescaler
315
Trigger Multiplexer
315
Table 12-1 Pre-Scaler Division Ratios
315
Table 12-2 6 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits
315
Operating Mode
316
Figure 12-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
317
Figure 12-4 PTIM Output Waveform, Single Counting Mode Configuration
318
Figure 12-5 LPTIM Output Waveform, Single Counting Mode Configuration and Set-Once Mode Activated
318
Timeout Function
319
Waveform Generation
319
Register Update
320
Figure 12-6 Waveform Generation
320
Counter Mode
321
Timer Enable
321
Encoder Mode
321
Non-Orthogonal Encoder Mode
323
Figure 12-7 Encoder Mode Counting Sequence
323
LPTIM Interrupts
324
Figure 12-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally
324
Figure 12-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working
324
LPTIM Registers
325
LPTIM Register Overview
325
LPTIM Interrupt and Status Register (LPTIM_INTSTS)
326
LPTIM Interrupt Clear Register (LPTIM_INTCLR)
327
LPTIM Interrupt Enable Register (LPTIM_INTEN)
327
LPTIM Configuration Register (LPTIM_CFG)
328
LPTIM Control Register (LPTIM_CTRL)
331
LPTIM Compare Register (LPTIM_COMP)
332
LPTIM Auto-Reload Register (LPTIM_ARR)
332
LPTIM Counter Register (LPTIM_CNT)
333
Independent Watchdog (IWDG)
334
Introduction
334
Main Features
334
Function Description
335
Register Access Protection
335
Figure 13-1 Functional Block Diagram of the Independent Watchdog Module
335
Debug Mode
336
User Interface
336
Operate Flow
336
IWDG Registers
337
IWDG Register Overview
337
IWDG Key Register (IWDG_KEY)
337
Table 13-1 IWDG Counting Maximum and Minimum Reset Time
337
Table 13-2 IWDG Register Overview
337
IWDG Pre-Scaler Register (IWDG_PREDIV)
338
IWDG Reload Register (IWDG_RELV)
338
IWDG Status Register (IWDG_STS)
339
Window Watchdog (WWDG)
340
Introduction
340
Main Features
340
Function Description
340
Figure 14-1 Watchdog Block Diagram
340
Timing for Refresh Watchdog and Interrupt Generation
341
Figure 14-2 Refresh Window and Interrupt Timing of WWDG
341
Debug Mode
342
User Interface
342
WWDG Configuration Flow
342
Table 14-1 Maximum and Minimum Counting Time of WWDG
342
WWDG Registers
343
WWDG Register Overview
343
WWDG Control Register (WWDG_CTRL)
343
WWDG Config Register (WWDG_CFG)
343
Table 14-2 WWDG Register Overview
343
WWDG Status Register (WWDG_STS)
344
Analog to Digital Conversion (ADC)
345
Introduction
345
Main Features
345
Single Conversion
345
Function Description
346
Figure 15-1 Block Diagram of a Single ADC
347
ADC Clock
348
Table 15-1 ADC Pins
348
ADC Switch Control
349
Channel Selection
349
Figure 15-2 ADC Clock
349
Internal Channel
350
Single Conversion Mode
350
Continuous Conversion Mode
350
Timing Diagram
351
Analog Watchdog
351
Figure 15-3 Timing Diagram
351
Scan Mode
352
Injection Channel Management
352
Table 15-2 Analog Watchdog Channel Selection
352
Discontinuous Mode
353
Figure 15-4 Injection Conversion Delay
353
Data Aligned
354
Programmable Channel Sampling Time
354
Table 15-3 Right-Aligned Data
354
Table 15-4 Left-Aligned Data
354
Externally Triggered Conversion
355
Table 15-5 ADC Is Used for External Triggering of Regular Channels
355
Table 15-6 ADC Is Used for External Triggering of Injection Channels
355
DMA Requests
356
Temperature Sensor
356
Temperature Sensor Using Flow
357
Figure 15-5 Temperature Sensor and VREFINT Diagram of the Channel
357
ADC Interrupt
358
ADC Registers
358
ADC Register Overview
358
Table 15-7 ADC Interrupt
358
Table 15-8 ADC Register Overview
358
ADC Status Register (ADC_STS)
359
ADC Control Register 1 (ADC_CTRL1)
360
ADC Control Register 2 (ADC_CTRL2)
363
ADC Sampling Time Register 1 (ADC_SAMPT1)
365
ADC Sampling Time Register 2 (ADC_ SAMPT2)
365
ADC Sampling Time Register 3 (ADC_SAMPT3)
366
ADC Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1
367
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
367
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
367
ADC Regular Sequence Register 1 (ADC_RSEQ1)
368
ADC Regular Sequence Register 2 (ADC_RSEQ2)
368
ADC Regular Sequence Register 3 (ADC_RSEQ3)
369
ADC Injection Sequence Register (ADC_JSEQ)
370
ADC Injection Data Register X (Adc_Jdatx) (X= 1
370
ADC Regulars Data Register (ADC_DAT)
371
ADC Control Register 3 (ADC_CTRL3)
371
Comparator (COMP)
373
COMP System Connection Block Diagram
373
COMP Features
374
Figure 16-1 Comparator System Connection Diagram
374
COMP Configuration Process
375
COMP Working Mode
376
Window Mode
376
Independent Comparator
376
Comparator Interconnection
376
Interrupt
378
COMP Register
378
COMP Register Overview
378
Table 16-1 COMP Register Overview
378
COMP Interrupt Enable Register (COMP_INTEN)
379
COMP Interrupt Register (COMP_INTSTS)
380
COMP Window Mode Enable Register(COMP_WINMODE)
380
COMP Lock Register(COMP_LOCK)
381
COMP1 Control Register (COMP1_CTRL)
382
COMP1 Filter Control Register (COMP1_FILC)
383
COMP1 Filter Frequency Division Register (COMP1_FILP)
384
COMP2 Control Register (COMP2_CTRL)
384
COMP2 Filter Control Register (COMP2_FILC)
386
COMP2 Filter Frequency Division Register (COMP2_FILP)
387
COMP3 Control Register (COMP3_CTRL)
387
COMP3 Filter Control Register (COMP3_FILC)
389
COMP3 Filter Frequency Division Register (COMP3_FILP)
389
COMP Reference Input Compare Voltage Register (COMP_INVREF)
390
C Interface
391
Introduction
391
Main Features
391
Function Description
391
SDA and SCL Line Control
392
Software Communication Process
392
Figure 17-1 I2C Functional Block Diagram
393
Start and Stop Conditions
393
Figure 17-2 I2C Bus Protocol
393
Clock Synchronization and Arbitration
393
Figure 17-3 Slave Transmitter Transfer Sequence Diagram
396
Figure 17-4 Slave Receiver Transfer Sequence Diagram
397
Figure 17-5 Master Transmitter Transfer Sequence Diagram
399
Figure 17-6 Master Receiver Transfer Sequence Diagram
401
Error Conditions Description
402
DMA Application
403
Transmit Process
403
Receive Process
404
Packet Error Check
404
Smbus
405
Table 17-1 Comparison between Smbus and I2C
405
Device Identification
406
Bus Protocol
406
Address Resolution Protocol
406
Debug Mode
407
Interrupt Request
407
Table 17-2 I 2 C Interrupt Request
407
I2C Registers
408
I2C Register Overview
408
Table 17-3 I2C Register Overview
408
I2C Control Register 1 (I2C_CTRL1)
409
I2C Control Register 2 (I2C_CTRL2)
411
I2C Own Address Register 1 (I2C_OADDR1)
412
I2C Own Address Register 2 (I2C_OADDR2)
413
I2C Data Register (I2C_DAT)
413
I2C Status Register 1 (I2C_STS1)
414
I2C Status Register 2 (I2C_STS2)
417
I2C Clock Control Register (I2C_CLKCTRL)
418
I2C Rise Time Register (I2C_TMRISE)
419
Universal Synchronous Asynchronous Receiver Transmitter (USART)
421
Introduction
421
Main Features
421
Functional Block Diagram
422
Function Description
422
Figure 18-1 USART Block Diagram
422
USART Frame Format
423
Transmitter
424
Figure 18-2 Word Length = 8 Setting
424
Figure 18-3 Word Length = 9 Setting
424
Table 18-1 Stop Bit Configuration
425
Figure 18-4 Configuration Stop Bit
425
Figure 18-5 Transmisson Delay
426
Single Byte Communication
427
Figure 18-6 TXC/TXDE Changes During Transmission
427
Receiver
428
Figure 18-7 Start Bit Detection
428
Framing Error
430
Overrun Error
431
Table 18-2 Data Sampling for Noise Detection
431
Generation of Fractional Baud Rate
432
Receiver's Tolerance Clock Deviation
433
Table 18-3 Error Calculation When Setting Baud Rate
433
Parity Control
434
Table 18-4 When Div_Decimal = 0. Tolerance of USART Receiver
434
Table 18-5 When Div_Decimal != 0. Tolerance of USART Receiver
434
Table 18-6 Frame Format
434
DMA Application
435
Figure 18-8 Transmission Using DMA
436
Hardware Flow Control
437
Figure 18-9 Reception Using DMA
437
Figure 18-10 Hardware Flow Control between Two USART
438
Figure 18-11 RTS Flow Control
438
Multiprocessor Communication
439
Idle Line Detection
439
Figure 18-12 CTS Flow Controls
439
Figure 18-13 Mute Mode Using Idle Line Detection
440
Synchronous Mode
441
Figure 18-14 Mute Mode Detected Using Address Mark
441
Figure 18-15 USART Synchronous Transmission Example
442
Figure 18-16 USART Data Clock Timing Example (WL=0)
443
Figure 18-17 USART Data Clock Timing Example (WL=1)
444
Figure 18-18 RX Data Sampling / Holding Time
444
Single-Wire Half-Duplex Mode
445
Irda SIR ENDEC Mode
445
Irda Low Power Mode
446
Figure 18-19 Irdasirendec-Block Diagram
446
LIN Mode
447
Figure 18-20 Irda Data Modulation (3/16)-Normal Mode
447
Figure 18-21 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
448
Smartcard Mode (ISO7816)
449
Figure 18-22 Break Detection and Framing Error Detection in LIN Mode
449
Figure 18-23 ISO7816-3 Asynchronous Protocol
450
Interrupt Request
451
Table 18-7 USART Interrupt Request
451
Figure 18-24 Use 1.5 Stop Bits to Detect Parity Errors
451
Mode Support
452
USART Register
452
USART Register Overview
452
Table 18-8 USART Mode Setting
452
Table 18-9 USART Register Overview
452
USART Status Register (USART_STS)
453
USART Data Register (USART_DAT)
455
USART Baud Rate Register (USART_BRCF)
456
USART Control Register 1 Register (USART_CTRL1)
456
USART Control Register 2 Register (USART_CTRL2)
458
USART Control Register 3 Register (USART_CTRL3)
460
USART Guard Time and Prescaler Register (USART_GTP)
461
Low Power Universal Asynchronous Receiver Transmitter (LPUART)
463
Introduction
463
Main Features
463
Functional Block Diagram
464
Function Description
464
Figure 19-1 LPUART Block Diagram
464
LPUART Frame Format
465
Transmitter
465
Figure 19-2 Frame Format
465
Receiver
467
Figure 19-3 TXC Changes During Transmission
467
Fractional Baud Rate Generation
469
Table 19-1 Data Sampling for Noise Detection
469
Figure 19-4 Data Sampling for Noise Detection
469
Parity Control
471
DMA Application
471
Table 19-2 Parity Frame Format
471
Figure 19-5 Sending Using DMA
472
Hardware Flow Control
473
Figure 19-6 Receiving with DMA
473
Figure 19-7 Hardware Flow Control between Two LPUART
473
Figure 19-8 RTS Flow Control
474
Low Power Wake up
475
Interrupt Request
475
Table 19-3 LPUART Interrupt Requests
475
Figure 19-9 CTS Flow Control
475
LPUART Registers
476
LPUART Register Overview
476
LPUART Status Register (LPUART_STS)
476
Table 19-4 LPUART Register Overview
476
LPUART Interrupt Enable Register (LPUART_INTEN)
477
LPUART Control Register (LPUART_CTRL)
478
LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1)
479
LPUART Data Register (LPUART_DAT)
480
LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2)
480
LPUART Wake up Data Register (LPUART_WUDAT)
481
Serial Peripheral Interface/Inter-IC Sound (SPI/ I2S)
482
SPI Introduction
482
SPI and I2S Main Features
482
SPI Features
482
I2S Features
482
SPI Function Description
483
General Description
483
Figure 20-1 SPI Block Diagram
483
Figure 20-2 Selective Management of Hardware/Software
484
Figure 20-3 Master and Slave Applications
485
Data Format
486
SPI Work Mode
486
Figure 20-4 Data Clock Timing Diagram
486
Figure 20-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in
487
Figure 20-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode
488
Figure 20-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode
489
Figure 20-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in
490
Figure 20-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit-Only Mode
490
Status Flag
492
Figure 20-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted
492
Turn off the SPI
493
SPI Communication Using DMA
494
CRC Calculation
495
Figure 20-11 Transmission Using DMA
495
Figure 20-12 Reception Using DMA
495
Error Flag
496
SPI Interrupt
497
Table 20-1 SPI Interrupt Request
497
I2S Function Description
498
Figure 20-13 I S Block Diagram
498
Supported Audio Protocols
499
Figure 20-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
500
Figure 20-15 I 2 S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
500
Right Channel
500
Figure 20-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
502
Figure 20-18 MSB Aligns 24-Bit Data, CLKPOL = 0
502
Figure 20-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
503
Figure 20-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
503
Figure 20-21 LSB Aligns 24-Bit Data, CLKPOL = 0
504
Figure 20-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
504
Figure 20-23 PCM Standard Waveform (16 Bits)
505
Figure 20-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
505
Clock Generator
506
Figure 20-25 I 2 S Clock Generator Structure
506
Figure 20-26 Audio Sampling Frequency Definition
506
I2S Send and Receive Sequence
507
Table 20-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency
507
Status Flag
509
Error Flag
510
I2S Interrupt
510
Table 20-3 I 2 S Interrupt Request
510
DMA Function
511
SPI and I2S Register Description
511
SPI Register Overview
511
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
511
Table 20-4 SPI Register Overview
511
SPI Control Register 2 (SPI_CTRL2)
514
SPI Status Register (SPI_STS)
515
SPI Data Register (SPI_DAT)
516
SPI CRC Polynomial Register (SPI_CRCPOLY)
516
Mode)
516
Mode)
517
SPI RX CRC Register (SPI_CRCRDAT)
517
SPI TX CRC Register（Spi_ CRCTDAT
517
SPI_ I 2 S Configuration Register（Spi_I2Scfg
518
SPI_I 2 S Prescaler Register (SPI_I2SPREDIV)
519
Real-Time Clock (RTC)
521
Description
521
Specification
521
Table 21-1 RTC Feature Support
521
RTC Function Description
523
RTC Block Diagram
523
Figure 21-1 RTC Block Diagram
523
Gpios of RTC
524
RTC Register Write Protection
524
RTC Clock and Prescaler
524
RTC Calendar
525
Calendar Initialization and Configuration
525
Calendar Reading
526
Calibration Clock Output
527
Programmable Alarms
527
Alarm Configuration
527
Alarm Output
527
Periodic Automatic Wakeup
528
Wakeup Timer Configuration
528
Timestamp Function
528
Tamper Detection
529
Daylight Saving Time Configuration
530
RTC Sub-Second Register Shift
530
RTC Digital Clock Precision Calibration
530
RTC Low Power Mode
531
RTC Registers
532
RTC Register Overview
532
Table 21-2 RTC Register Overview
532
RTC Calendar Time Register (RTC_TSH)
533
RTC Calendar Date Register (RTC_DATE)
534
RTC Control Register (RTC_CTRL)
534
RTC Initial Status Register (RTC_INITSTS)
537
RTC Prescaler Register (RTC_PRE)
539
RTC Wakeup Timer Register (RTC_WKUPT)
539
RTC Alarm a Register (RTC_ALARMA)
540
RTC Alarm B Register (RTC_ ALARMB)
541
RTC Write Protection Register (RTC_WRP)
542
RTC Sub-Second Register (RTC_SUBS)
542
RTC Shift Control Register (RTC_SCTRL)
543
RTC Timestamp Time Register (RTC_TST)
543
RTC Timestamp Date Register (RTC_TSD)
544
RTC Timestamp Sub-Second Register (RTC_TSSS)
545
RTC Calibration Register (RTC_CALIB)
545
RTC Tamper Configuration Register（Rtc_Tmpcfg
546
RTC Alarm a Sub-Second Register (RTC_ALRMASS)
548
RTC Alarm B Sub-Second Register (RTC_ALRMBSS)
549
Operational Amplifier（Opamp
550
OPAMP Features
550
OPAMP Function Description
551
OPAMP Working Mode
551
OPAMP External Amplification Mode
551
Figure 22-1 Block Diagram of OPAMP Connection Diagram
551
OPAMP Follow Mode
552
Figure 22-2 OPAMP External Amplification Mode
552
OPAMP Internal Programmable Gain (PGA) Mode
553
Figure 22-3 OPAMP Follow Mode
553
OPAMP Independent Write Protection
554
OPAMP TIMER Controls the Switching Mode
554
Figure 22-4 Internal Programmable Gain Mode
554
OPAMP Registers
555
OPAMP Registers Overview
555
Table 22-1 OPAMP Register Overview
555
OPAMP Control Status Register (OPAMP_CS)
556
OPAMP Lock Register (OPAMP_LOCK)
557
Beeper
558
Introduction
558
Function Description
558
Beeper Registers
558
Beeper Register Overview
558
Beeper Control Register (BEEPER_CTRL)
558
Table 23-1 Beeper Register Overview
558
Arithmetic Units (HDIV and SQRT)
560
Introduction to HDIV and SQRT
560
HDIV and SQRT Function Description
560
HDIV Registers
560
HDIV Register Overview
560
Table 24-1 HDIV Register Overview
560
HDIV Control Status Register (HDIV_CTRLSTS)
561
HDIV Dividend Register (HDIV_DIVIDEND)
561
HDIV Divisor Register (HDIV_DIVISOR)
562
HDIV Quotient Register (HDIV_QUOTIENT)
562
HDIV Remainder Register (HDIV_REMAINDER)
562
HDIV Divide by Zero Register (HDIV_DIVBY0)
563
SQRT Registers
563
SQRT Register Overview
563
Table 24-2 SQRT Register Overview
563
SQRT Control Status Register (SQRT_CTRLSTS)
564
SQRT Radicand Register (SQRT_RADICAND)
564
SQRT Square Root Register (SQRT_ROOT)
565
Controller Area Network (CAN)
566
Introduction to CAN
566
Main Features of CAN
566
CAN Overall Introduction
566
CAN Module
567
CAN Working Mode
567
Figure 25-1 Topology of CAN Network
567
Normal Mode
568
Initialization Mode
568
Sleep Mode (Low Power)
568
Send Mailbox
569
Receiving Filter
569
Receive FIFO
569
Figure 25-2 CAN Working Mode
569
CAN Test Mode
570
Loopback Mode
570
Figure 25-3 Single CAN Block Diagram
570
Silent Mode
571
Figure 25-4 Loopback Mode
571
Figure 25-5 Silent Mode
572
CAN Debugging Mode
573
CAN Function Description
573
Send Processing
573
Figure 25-6 Loopback Silent Mode
573
Time Triggered Communication Mode
574
Non-Automatic Retransmission Mode
574
Receiving Management
575
Figure 25-7 Send Mailbox Status
575
Figure 25-8 Receive FIFO Status
576
Identifier Filtering
577
Figure 25-9 Filter Bit Width Setting-Register Organization
578
Table 25-1 Examples of Filter Numbers
579
Message Storage
580
Figure 25-10 Examples of Filter Mechanisms
580
Bit Time Characteristic
581
Table 25-2 Send Mailbox Register List
581
Table 25-3 Receive Mailbox Register List
581
Figure 25-11 Bit Sequence
582
Figure 25-12 Various CAN Frames
583
CAN Interrupt
584
Figure 25-13 Event Flag and Interrupt Generation
584
Error Management
585
Bus-Off Recovery
585
Figure 25-14 CAN Error State Diagram
585
CAN Configuration Flow
586
CAN Register File
587
Register Description
587
CAN Register Address Overview
588
CAN Control and Status Register
592
CAN Mailbox Register
603
CAN Filter Register
609
Cryptographic Algorithm Hardware Acceleration Engine (SAC)
614
Debug Support (DBG)
615
Overview
615
Figure 27-1 N32G032 Level and Cortex®-M0 Level Debugging Block Diagram
615
SWD Function
616
Pin Assignment
616
Unique Device Serial Number (UID)
617
Introduction
617
UID Register
617
UCID Register
617
DBGMCU_ID Register
617
Version History
619
Notice
620

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