Retention Domain Control Register (Rcc_Rdctrl) - Nations N32G43 Series User Manual

Bit Field Name
10 Reserved
9 UCDR300MSEL
8 USBXTALESS
7 UCDREN
6:0 Reserved

Retention Domain Control Register (RCC_RDCTRL)

Address offset: 0x34
Reset value: 0x0000 0000
Bit Field Name
31:12 Reserved
11 LPUARTRST
10 LPTIMRST
9:8 Reserved
7 LPUARTEN
Description
00010: TRNG 1M clock source divided by 4
00011: TRNG 1M clock source divided by 6
00100: TRNG 1M clock source divided by 8
...
11111: TRNG 1M clock source divided by 62
Notes: TRNG clock should be less than or equal to 4M after frequency division
Reserved, the reset value must be maintained.
UCDR 300M clock source selection
0: OSC300M
1: PLL VCO clock (288M)
USB external crystal oscillator selection mode
0: USB has external crystal oscillator mode
1: USB without external crystal oscillator mode
UCDR enable
0: UCDR bypass
1: UCDR enable
Reserved, the reset value must be maintained.
Description
Reserved, the reset value must be maintained.
LPUART reset.
Set or cleared by software.
0: Clear reset
1: Reset LPUART
LPTIM reset.
Set or cleared by software.
0: Clear reset
1: Reset LPTIM
Reserved, the reset value must be maintained.
LPUART clock enable.
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