Counter Mode; Figure 10-2 Counter Timing Diagram With Prescaler Division Change From 1 To 4 - Nations N32G43 Series User Manual

starts counting one clock cycle after the TIMx_CTRL1.CNTEN bit is set.
Prescaler description
The TIMx_PSC register consists of a 16-bit counter that can be used to divide the counter clock frequency by any
factor between 1 and 65536. It can be changed on the fly as it is buffered. The prescaler value is only taken into
account at the next update event.

Figure 10-2 Counter timing diagram with prescaler division change from 1 to 4

Timer Clock = CK_CNT
Counter register
Update event（UEV）
Prescaler controller register
Prescaler counter
Prescaler buffer

Counter mode

Up-counting mode
In up-counting mode, the counter will count from 0 to the value of the register TIMx_AR, then it resets to 0. And a
counter overflow event is generated.
If the TIMx_CTRL1.UPRS bit (select update request) and the TIMx_EVTGEN.UDGN bit are set, an update event
(UEV) will generate. And TIMx_STS.UDITF will not be set by hardware, therefore, no update interrupts or update
DMA requests are generated. This setting is used in scenarios where you want to clear the counter but do not want to
generate an update interrupt.
Depending on the update request source is configured in the TIMx_CTRL1.UPRS, When an update event occurs, the
TIMx_STS.UDITF is set, all registers are updated:

The repetition counter reloads the contents of the TIMx_REPCNT
CNTEN
CK_PSC
88
87
0
Write a new value in TIMx_PSC
89 8A 8B 8C 00
3
0
0 1 2
0
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