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Nations N32G03 Series Manuals
Manuals and User Guides for Nations N32G03 Series. We have
2
Nations N32G03 Series manuals available for free PDF download: User Manual
Nations N32G03 Series User Manual (620 pages)
32-bit ARM Cortex-M0
Brand:
Nations
| Category:
Microcontrollers
| Size: 11 MB
Table of Contents
Table of Contents
2
Abbreviations in the Text
30
List of Abbreviations for Registers
30
Available Peripherals
30
Memory and Bus Architecture
31
System Architecture
31
Bus Architecture
31
Figure 2-1 Bus Architecture
32
Bus Address Mapping
33
Table 2-1 List of Peripheral Register Addresses
34
Figure 2-2 Bus Address Map
34
Boot Management
36
Memory System
37
FLASH Specification
37
Table 2-2 List of Boot Mode
37
Table 2-3 Flash Bus Address List
38
Option Byte
41
Table 2-4 Option Byte List
42
Write Protect
43
Table 2-5 Read Protection Configuration List
43
Table 2-6 Flash Read-Write-Erase
45
Sram
49
FLASH Register Description
50
Table 2-7 FLASH Register Overview
50
Power Control (PWR)
57
General Description
57
Power Supply
57
Power Supply Supervisor
58
Figure 3-1 Power Supply Block Diagram
58
Figure 3-2 Power on Reset/Power down Reset Waveform
59
Programmable Voltage Detector (PVD)
59
Power Modes
60
Table 3-1 Power Modes
60
Figure 3-3 PVD Threshold Diagram
60
Table 3-2 Peripheral Running Status
61
LPRUN Mode
62
SLEEP Mode
63
Enter SLEEP Mode
63
Exit SLEEP Mode
63
STOP Mode
63
PD Mode
64
Debug Support
65
Low Power Mode Debug Support
65
Peripheral Debug Support
65
PWR Registers
65
PWR Register Overview
65
Table 3-3 PWR Register Overview
65
Power Control Register (PWR_CTRL)
66
Power Control Status Register (PWR_CTRLSTS)
67
Power Control Register 2 (PWR_CTRL2)
69
Power Control Register 3 (PWR_CTRL3)
69
Power Control Register 4 (PWR_CTRL4)
69
Power Control Register 5 (PWR_CTRL5)
70
Power Control Register 6 (PWR_CTRL6)
71
Debug Control Register (DBG_CTRL)
71
Reset and Clock Control (RCC)
74
Reset Control Unit
74
Power Reset
74
System Reset
74
Software Reset
75
Low-Power Management Reset
75
Figure 4-1 System Reset Generation
75
Clock Control Unit
76
Clock Tree Diagram
78
Figure 4-2 Clock Tree
78
HSE Clock
79
Figure 4-3 HSE Clock Source
79
External Crystal/Ceramic Resonator (HSE Crystal)
79
HSI Clock
80
PLL Clock
80
LSE Clock
81
LSI Clock
81
Figure 4-4 PLL Clock Configuration
81
LSI Calibration
82
System Clock (SYSCLK) Selection
82
Clock Security System (CLKSS)
82
RTC Clock
83
Watchdog Clock
83
LPUART Clock
83
LPTIME Clock
83
Clock Output(MCO)
83
RCC Registers
84
RCC Register Overview
84
Table 4-1 RCC Register Overview
84
Clock Control Register (RCC_CTRL)
85
Clock Configuration Register (RCC_CFG)
87
Clock Interrupt Register (RCC_CLKINT)
89
APB2 Peripheral Reset Register (RCC_APB2PRST)
92
APB1 Peripheral Reset Register (RCC_APB1PRST)
94
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
96
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
97
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
99
Low Speed Clock Control Register (RCC_LSCTRL)
101
Control/Status Register (RCC_CTRLSTS)
102
AHB Peripheral Reset Register (RCC_AHBPRST)
104
Clock Configuration Register 2(RCC_CFG2)
105
EMC Control Register 3 (RCC_EMCCTRL)
107
GPIO and AFIO
111
Summary
111
Function Description
112
I/O Mode Configuration
112
Table 5-1 I/O Port Configuration Table
112
Figure 5-1 Basic Structure of I/O Ports
112
Table 5-2 I/O List of Functional Features of the Pin
113
Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode
114
Figure 5-3 Output Mode
115
Figure 5-4 Alternate Function Mode
116
Figure 5-5 Analog Function Mode with High Impedance
116
Status after Reset
117
Individual Bit Setting and Bit Clearing
117
External Interrupt /Wakeup Line
117
Alternate Function
117
Table 5-3 I/O List of Functional Features of the Pin
118
Table 5-4 TIM1 Alternate Function I/O Remapping
118
Table 5-5 TIM8 Alternate Function I/O Remapping
119
Table 5-6 TIM3 Alternate Function I/O Remapping
120
Table 5-7 TIM4 Alternate Function I/O Remapping
120
Table 5-8 LPTIM Alternate Function I/O Remapping
121
Table 5-9 CAN Alternate Function I/O Remapping
121
Table 5-10 USART1 Alternate Function I/O Remapping
122
Table 5-11 USART2 Alternate Function I/O Remapping
122
Table 5-12 UART5 Alternate Function I/O Remapping
123
Table 5-13 UART6 Alternate Function I/O Remapping
123
Table 5-14 LPUART1 Alternate Function I/O Remapping
123
Table 5-15 LPUART2 Alternate Function I/O Remapping
124
Table 5-16 I2C1 Alternate Function I/O Remapping
124
Table 5-17 I2C2 Alternate Function I/O Remapping
125
Table 5-18 SPI1/I2S1 Alternate Function I/O Remapping
126
Table 5-19 SPI2 Alternate Function I/O Remapping
126
Table 5-20 SPI3 Alternate Function I/O Remapping
127
Table 5-21 COMP1 Alternate Function I/O Remapping
127
Table 5-22 COMP2 Alternate Function I/O Remapping
127
Table 5-23 COMP3 Alternate Function I/O Remapping
127
Table 5-24 BEEPER1 Alternate Function I/O Remapping
128
Table 5-25 BEEPER2 Alternate Function I/O Remapping
128
Table 5-26 EVENTOUT Alternate Function I/O Remapping
128
Table 5-27 RTC Alternate Function I/O Remapping
129
Table 5-28 PVD Alternate Function I/O Remapping
129
Table 5-29 RCC Alternate Function I/O Remapping
129
Table 5-30 OSC_IN/OSC_OUT Alternate Function I/O Remapping
129
Table 5-31 OSC32 Alternate Function Remapping
129
Table 5-32 OSC Alternate Function Remapping
130
Table 5-33 ADC External Trigger Injection Conversion Alternate Function Remapping
130
Table 5-34 ADC External Trigger Regular Conversion Alternate Function Remapping
130
I/O Configuration of Peripherals
131
Table 5-35 TIM4_CH2 Alternate Function Remapping
131
Table 5-36 IO Signal Dual Voltage Levels Configuration
131
Table 5-37 ADC
131
Table 5-38 PVD
131
Table 5-39 TIM1/TIM8
131
Table 5-40 TIM3 and LPTIM
131
Table 5-41 CAN
132
Table 5-42 USART
132
Table 5-43 LPUART
132
Table 5-44 I2C
132
Table 5-45 SPI
132
GPIO Locking Mechanism
133
Table 5-46 COMP
133
Table 5-47 BEEPER
133
Table 5-48 Other
133
GPIO Registers
134
GPIO Register Overview
134
Table 5-49 GPIO Register Overview
134
GPIO Port Mode Description Register (Gpiox_Pmode)
135
GPIO Port Type Definition (Gpiox_Potype)
136
GPIO Slew Rate Configuration Register (Gpiox_Sr)
137
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupd)
137
GPIO Port Input Data Register (Gpiox_Pid)
138
GPIO Port Output Data Register (Gpiox_Pod)
138
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)
139
GPIO Port Configuration Lock Register (Gpiox_ PLOCK)
140
GPIO Alternate Function Low Register (Gpiox_Afl)
141
GPIO Alternate Function High Register (Gpiox_Afh)
141
GPIO Port Bit Clear Register (Gpiox_Pbc)
142
GPIO Driver Strength Configuration Register (Gpiox_ DS)
143
AFIO Registers
143
AFIO Register Overview
143
AFIO Configuration Register (AFIO_CFG)
144
Table 5-50 AFIO Register Overview
144
AFIO External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1)
145
AFIO External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2)
146
AFIO External Interrupt Configuration Register 3 (AFIO_EXTI_CFG3)
147
AFIO External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4)
148
Interrupts and Events
149
Nested Vectored Interrupt Controller
149
Systick Calibration Value Register
149
Interrupt and Exception Vectors
149
Table 6-1 Vector Table
149
External Interrupt/Event Controller (EXTI)
151
Introduction
151
Main Features
151
Functional Description
152
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram
152
EXTI Line Mapping
153
Figure 6-2 External Interrupt Generic I/O Mapping
153
EXTI Registers
155
EXTI Register Overview
155
Interrupt Mask Register(EXTI_IMASK)
155
Table 6-2 EXTI Register Overview
155
Event Mask Register(EXTI_EMASK)
156
Rising Edge Trigger Selection Register(EXTI_RT_CFG)
156
Falling Edge Trigger Selection Register(EXTI_FT_CFG)
157
Software Interrupt Enable Register(EXTI_SWIE)
157
Interrupt Request Pending Register(EXTI_PEND)
158
RTC Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
158
DMA Controller
159
Introduction
159
Main Features
159
Block Diagram
160
Function Description
160
DMA Operation
160
Figure 7-1 DMA Block Diagram
160
Channel Priority and Arbitration
161
DMA Channels and Number of Transfers
161
Programmable Data Bit Width, Alignment and Endians
161
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
162
Peripheral/Memory Address Incrementation
163
Channel Configuration Procedure
163
Flow Control
164
Table 7-2 Flow Control Table
164
Circular Mode
165
Error Management
165
Interrupt
165
DMA Request Mapping
166
Table 7-3 DMA Interrupt Request
166
Table 7-4 DMA Request Mapping
166
DMA Registers
167
DMA Register Overview
167
Table 7-5 DMA Register Overview
167
DMA Interrupt Status Register (DMA_INTSTS)
168
DMA Interrupt Flag Clear Register (DMA_INTCLR)
169
DMA Channel X Configuration Register (Dma_Chcfgx)
170
DMA Channel X Transfer Number Register (Dma_Txnumx)
171
DMA Channel X Peripheral Address Register (Dma_Paddrx)
172
DMA Channel X Memory Address Register (Dma_Maddrx)
172
DMA Channel X Channel Request Select Register (Dma_Chselx)
173
CRC Calculation Unit
174
CRC Introduction
174
CRC Main Features
174
CRC32 Module
174
CRC16 Module
174
CRC Function Description
175
Crc32
175
Crc16
175
Figure 8-1 CRC Calculation Unit Block Diagram
175
CRC Registers
176
CRC Register Overview
176
CRC32 Data Register (CRC_CRC32DAT)
176
CRC32 Independent Data Register (CRC_CRC32IDAT)
176
Table 8-1 CRC Register Overview
176
CRC32 Control Register (CRC_CRC32CTRL)
177
CRC16 Control Register (CRC_CRC16CTRL)
177
CRC16 Input Data Register (CRC_CRC16DAT)
178
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
178
LRC Result Register (CRC_LRC)
179
Advanced-Control Timers (TIM1 and TIM8)
180
TIM1 and TIM8 Introduction
180
Main Features of TIM1 and TIM8
180
TIM1 and TIM8 Function Description
181
Time-Base Unit
181
Figure 9-1 Block Diagram of TIM1 and TIM8
181
Prescaler Description
182
Counter Mode
182
Figure 9-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
182
Up-Counting Mode
182
Figure 9-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
184
Down-Counting Mode
186
Figure 9-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
186
Center-Aligned Mode
186
Figure 9-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
187
Figure 9-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
188
Counter Underflow
188
Repetition Counter
188
Figure 9-8 Repeat Count Sequence Diagram in Down-Counting Mode
189
Figure 9-9 Repeat Count Sequence Diagram in Up-Counting Mode
190
Figure 9-10 Repeat Count Sequence Diagram in Center-Aligned Mode
190
Clock Selection
191
Figure 9-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
191
Figure 9-12 TI2 External Clock Connection Example
192
Figure 9-13 Control Circuit in External Clock Mode 1
193
Figure 9-14 External Trigger Input Block Diagram
193
Capture/Compare Channels
194
Figure 9-15 Control Circuit in External Clock Mode 2
194
Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
195
Figure 9-17 Capture/Compare Channel 1 Main Circuit
196
Figure 9-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
196
Input Capture Mode
197
Figure 9-19 Output Part of Channelx (X= 4)
197
PWM Input Mode
198
Forced Output Mode
199
Figure 9-20 PWM Input Mode Timing
199
Output Compare Mode
200
PWM Mode
201
PWM Center-Aligned Mode
201
Figure 9-21 Output Compare Mode, Toggle on OC1
201
Figure 9-22 Center-Aligned PWM Waveform (AR=8)
202
Figure 9-23 Edge-Aligned PWM Waveform (APR=8)
203
One-Pulse Mode
204
Figure 9-24 Example of One-Pulse Mode
204
Clearing the Ocxref Signal on an External Event
205
Complementary Outputs with Dead-Time Insertion
206
Figure 9-25 Clearing the Ocxref of Timx
206
Figure 9-26 Complementary Output with Dead-Time Insertion
207
Break Function
208
Debug Mode
210
Timx and External Trigger Synchronization
210
Slave Mode: Reset Mode
210
Figure 9-27 Output Behavior in Response to a Break
210
Slave Mode: Trigger Mode
211
Figure 9-28 Control Circuit in Reset Mode
211
Slave Mode: Gated Mode
212
Figure 9-29 Control Circuit in Trigger Mode
212
Figure 9-30 Control Circuit in Gated Mode
213
Timer Synchronization
214
6-Step PWM Generation
214
Figure 9-31 Control Circuit in Trigger Mode + External Clock Mode2
214
Encoder Interface Mode
215
Figure 9-32 6-Step PWM Generation, COM Example (OSSR=1)
215
Table 9-1 Counting Direction Versus Encoder Signals
216
Figure 9-33 Example of Counter Operation in Encoder Interface Mode
216
Figure 9-34 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
217
Interfacing with Hall Sensor
218
Advanced-Control
219
Figure 9-35 Example of Hall Sensor Interface
219
Timx Register Description(X=1, 8)
220
Register Overview
220
Table 9-2 Register Overview
220
Control Register 1 (Timx_Ctrl1)
221
Control Register 2 (Timx_Ctrl2)
223
Slave Mode Control Register (Timx_Smctrl)
225
Table 9-3 Timx Internal Trigger Connection
227
Dma/Interrupt Enable Registers (Timx_Dinten)
228
Status Registers (Timx_Sts)
229
Event Generation Registers (Timx_Evtgen)
231
Capture/Compare Mode Register 1 (Timx_Ccmod1)
232
Capture/Compare Mode Register 2 (Timx_Ccmod2)
236
Capture/Compare Enable Registers (Timx_Ccen)
237
Table 9-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
239
Counters (Timx_Cnt)
240
Prescaler (Timx_Psc)
240
Auto-Reload Register (Timx_Ar)
241
Repeat Count Registers (Timx_Repcnt)
241
Capture/Compare Register 1 (Timx_Ccdat1)
242
Capture/Compare Register 2 (Timx_Ccdat2)
242
Capture/Compare Register 3 (Timx_Ccdat3)
243
Capture/Compare Register 4 (Timx_Ccdat4)
243
Break and Dead-Time Registers (Timx_Bkdt)
244
DMA Control Register (Timx_Dctrl)
246
DMA Transfer Buffer Register (Timx_Daddr)
246
Capture/Compare Mode Registers 3(Timx_Ccmod3)
247
Capture/Compare Register 5 (Timx_Ccdat5)
248
Capture/Compare Register 6 (Timx_Ccdat6)
248
General-Purpose Timers (TIM3 and TIM4)
249
General-Purpose Timers Introduction
249
Main Features of General-Purpose Timers
249
General-Purpose Timers Description
250
Time-Base Unit
250
Figure 10-1 Block Diagram of Timx(X=3 and 4
250
Counter Mode
251
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
251
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
252
Figure 9-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
253
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
253
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
254
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
255
Clock Selection
256
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
256
Figure 10-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
257
Figure 10-9 TI2 External Clock Connection Example
258
Figure 10-10 Control Circuit in External Clock Mode 1
259
Figure 10-11 External Trigger Input Block Diagram
259
Capture/Compare Channels
260
Figure 10-12 Control Circuit in External Clock Mode 2
260
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
261
Figure 10-14 Capture/Compare Channel 1 Main Circuit
262
Input Capture Mode
263
Figure 10-15 Output Part of Channelx (X = 1,2,3,4;Take Channel 4 as an Example
263
PWM Input Mode
264
Forced Output Mode
265
Output Compare Mode
265
Figure 10-16 PWM Input Mode Timing
265
PWM Mode
267
Figure 10-17 Output Compare Mode, Toggle on OC1
267
Figure 10-18 Center-Aligned PWM Waveform (AR=8)
268
Figure 10-19 Edge-Aligned PWM Waveform (APR=8)
269
One-Pulse Mode
270
Figure 10-20 Example of One-Pulse Mode
270
Clearing the Ocxref Signal on an External Event
271
Debug Mode
272
Timx and External Trigger Synchronization
272
Timer Synchronization
272
Figure 10-21 Control Circuit in Reset Mode
272
Figure 10-22 Block Diagram of Timer Interconnection
273
Figure 10-23 TIM3 Gated by OC1REF of TIM1
274
Figure 10-24 TIM3 Gated by Enable Signal of TIM1
275
Figure 10-25 Trigger TIM3 with an Update of TIM1
276
Encoder Interface Mode
277
Table 10-1 Counting Direction Versus Encoder Signals
277
Figure 10-26 Triggers Timers 1 and 3 Using the TI1 Input of TIM1
277
Figure 10-27 Example of Counter Operation in Encoder Interface Mode
278
Interfacing with Hall Sensor
279
Timx Register Description(X=3 and 4)
279
Register Overview
279
Table 10-2 Register Overview
279
Control Register 1 (Timx_Ctrl1)
281
Control Register 2 (Timx_Ctrl2)
283
Slave Mode Control Register (Timx_Smctrl)
284
Dma/Interrupt Enable Registers (Timx_Dinten)
286
Table 10-3 Timx Internal Trigger Connection
286
Status Registers (Timx_Sts)
287
Event Generation Registers (Timx_Evtgen)
289
Capture/Compare Mode Register 1 (Timx_Ccmod1)
290
Capture/Compare Mode Register 2 (Timx_Ccmod2)
293
Capture/Compare Enable Registers (Timx_Ccen)
295
Counters (Timx_Cnt)
296
Table 10-4 Output Control Bits of Standard Ocx Channel
296
Prescaler (Timx_Psc)
297
Auto-Reload Register (Timx_Ar)
297
Capture/Compare Register 1 (Timx_Ccdat1)
297
Capture/Compare Register 2 (Timx_Ccdat2)
298
Capture/Compare Register 3 (Timx_Ccdat3)
298
Capture/Compare Register 4 (Timx_Ccdat4)
299
DMA Control Register (Timx_Dctrl)
299
DMA Transfer Buffer Register (Timx_Daddr)
300
Basic Timers (TIM6)
302
Basic Timers Introduction
302
Main Features of Basic Timers
302
Basic Timers Description
302
Time-Base Unit
302
Figure 11-1 Block Diagram of Timx(X = 6
302
Counter Mode
303
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
303
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
304
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
305
Clock Selection
306
Debug Mode
306
Timx Register Description(X=6)
306
Figure 11-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
306
Register Overview
307
Control Register 1 (Timx_Ctrl1)
307
Table 11-1 Register Overview
307
Dma/Interrupt Enable Registers (Timx_Dinten)
308
Status Registers (Timx_Sts)
309
Event Generation Registers (Timx_Evtgen)
309
Counters (Timx_Cnt)
310
Prescaler (Timx_Psc)
310
Automatic Reload Register (Timx_Ar)
311
Low Power Timer (LPTIM)
312
Introduction
312
Main Features
312
Function Description
313
Block Diagram
313
LPTIM Reset and Clock
313
Figure 12-1 LPTIM Diagram
313
Glitch Filter
314
Figure 12-2 Glitch Filter Timing Diagram
314
Prescaler
315
Trigger Multiplexer
315
Table 12-1 Pre-Scaler Division Ratios
315
Table 12-2 6 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits
315
Operating Mode
316
Figure 12-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
317
Figure 12-4 PTIM Output Waveform, Single Counting Mode Configuration
318
Figure 12-5 LPTIM Output Waveform, Single Counting Mode Configuration and Set-Once Mode Activated
318
Timeout Function
319
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Nations N32G03 Series User Manual (559 pages)
32-bit ARM Cortex-M0
Brand:
Nations
| Category:
Microcontrollers
| Size: 9 MB
Table of Contents
Table of Contents
2
Abbreviations in the Text
27
List of Abbreviations for Registers
27
Available Peripherals
27
Memory and Bus Architecture
28
System Architecture
28
Bus Architecture
28
Figure 2-1 Bus Architecture
29
Bus Address Mapping
30
Figure 2-2 Bus Address Map
30
Table 2-1 List of Peripheral Register Addresses
31
Boot Management
32
Embedded Boot Loader
33
Memory System
33
FLASH Specification
33
Table 2-2 List of Boot Mode
33
Table 2-3 Flash Bus Address List
34
Option Byte
37
Table 2-4 Option Byte List
38
Write Protect
39
Table 2-5 Read Protection Configuration List
39
Table 2-6 Flash Read-Write-Erase
41
Sram
45
FLASH Register Description
46
Table 2-7 FLASH Register Overview
46
Power Control (PWR)
53
General Description
53
Power Supply
53
Power Supply Supervisor
54
Figure 3-1 Power Supply Block Diagram
54
Figure 3-2 Power on Reset/Power down Reset Waveform
55
Programmable Voltage Detector (PVD)
55
Nrst
56
Power Modes
56
Table 3-1 Power Modes
56
Figure 3-3 PVD Threshold Diagram
56
Table 3-2 Peripheral Running Status
57
LPRUN Mode
58
SLEEP Mode
59
Enter SLEEP Mode
59
Exit SLEEP Mode
59
STOP Mode
59
PD Mode
60
Debug Support
61
Low Power Mode Debug Support
61
Peripheral Debug Support
61
PWR Registers
61
PWR Register Overview
61
Table 3-3 PWR Register Overview
61
Power Control Register (PWR_CTRL)
62
Power Control Status Register (PWR_CTRLSTS)
63
Power Control Register 2 (PWR_CTRL2)
65
Power Control Register 3 (PWR_CTRL3)
65
Power Control Register 4 (PWR_CTRL4)
65
Power Control Register 5 (PWR_CTRL5)
66
Power Control Register 6 (PWR_CTRL6)
67
Debug Control Register (DBG_CTRL)
67
Reset and Clock Control (RCC)
70
Reset Control Unit
70
Power Reset
70
System Reset
70
Software Reset
71
Low-Power Management Reset
71
Clock Control Unit
72
Figure 4-1 System Reset Generation
72
Clock Tree Diagram
74
Figure 4-2 Clock Tree
74
HSE Clock
75
Figure 4-3 HSE Clock Source
75
External Crystal/Ceramic Resonator (HSE Crystal)
75
HSI Clock
76
PLL Clock
76
LSE Clock
77
LSI Clock
77
Figure 4-4 PLL Clock Configuration
77
System Clock (SYSCLK) Selection
78
Clock Security System (CLKSS)
78
RTC Clock
78
Watchdog Clock
78
LPUART Clock
78
LPTIME Clock
79
Clock Output(MCO)
79
RCC Registers
79
RCC Register Overview
79
Table 4-1 RCC Register Overview
79
Clock Control Register (RCC_CTRL)
81
Clock Configuration Register (RCC_CFG)
82
Clock Interrupt Register (RCC_CLKINT)
85
APB2 Peripheral Reset Register (RCC_APB2PRST)
88
APB1 Peripheral Reset Register (RCC_APB1PRST)
89
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
90
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
92
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
93
Low Speed Clock Control Register (RCC_LSCTRL)
95
Control/Status Register (RCC_CTRLSTS)
96
AHB Peripheral Reset Register (RCC_AHBPRST)
98
Clock Configuration Register 2(RCC_CFG2)
99
Table 5-25 ADC
100
EMC Control Register 3 (RCC_EMCCTRL)
101
GPIO and AFIO
104
Summary
104
Function Description
105
I/O Mode Configuration
105
Table 5-1 I/O Port Configuration Table
105
Figure 5-1 Basic Structure of I/O Ports
105
Table 5-2 I/O List of Functional Features of the Pin
106
Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode
107
Figure 5-3 Output Mode
108
Figure 5-4 Alternate Function Mode
109
Figure 5-5 Analog Function Mode with High Impedance
109
Status after Reset
110
Individual Bit Setting and Bit Clearing
110
External Interrupt /Wakeup Line
110
Alternate Function
110
Table 5-3 I/O List of Functional Features of the Pin
111
Table 5-4 TIM1 Alternate Function I/O Remapping
111
Table 5-5 TIM8 Alternate Function I/O Remapping
112
Table 5-6 TIM3 Alternate Function I/O Remapping
112
Table 5-7 LPTIM Alternate Function I/O Remapping
113
Table 5-8 USART1 Alternate Function I/O Remapping
113
Table 5-9 USART2 Alternate Function I/O Remapping
114
Table 5-10 LPUART Alternate Function I/O Remapping
114
Table 5-11 I2C1 Alternate Function I/O Remapping
115
Table 5-12 I2C2 Alternate Function I/O Remapping
115
Table 5-13 SPI1/I2S Alternate Function I/O Remapping
116
Table 5-14 SPI2 Alternate Function I/O Remapping
117
Table 5-15 COMP Alternate Function I/O Remapping
117
Table 5-16 BEEPER Alternate Function I/O Remapping
117
Table 5-17 EVENTOUT Alternate Function I/O Remapping
117
Table 5-18 RTC Alternate Function I/O Remapping
118
Table 5-19 RCC Alternate Function I/O Remapping
118
Table 5-20 OSC_IN/OSC_OUT Alternate Function I/O Remapping
118
Table 5-21 OSC32 Alternate Function Remapping
119
Table 5-22 OSC Alternate Function Remapping
119
Table 5-23 ADC External Trigger Injection Conversion Alternate Function Remapping
119
I/O Configuration of Peripherals
120
Table 5-24 ADC External Trigger Regular Conversion Alternate Function Remapping
120
Table 5-26 PVD
120
Table 5-27 TIM1/TIM8
120
Table 5-28 TIM3 and LPTIM
120
Table 5-29 USART
120
Table 5-30 LPUART
121
Table 5-31 I2C
121
Table 5-32 SPI
121
Table 5-33 COMP
121
GPIO Locking Mechanism
122
Table 5-34 BEEPER
122
Table 5-35 Other
122
GPIO Registers
123
GPIO Register Overview
123
Table 5-36 GPIO Register Overview
123
GPIO Port Mode Description Register (Gpiox_Pmode)
124
GPIO Port Type Definition (Gpiox_Potype)
125
GPIO Slew Rate Configuration Register (Gpiox_Sr)
125
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupd)
126
GPIO Port Input Data Register (Gpiox_Pid)
127
GPIO Port Output Data Register (Gpiox_Pod)
127
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)
128
GPIO Port Configuration Lock Register (Gpiox_ PLOCK)
129
GPIO Alternate Function Low Register (Gpiox_Afl)
129
GPIO Alternate Function High Register (Gpiox_Afh)
130
GPIO Port Bit Clear Register (Gpiox_Pbc)
131
GPIO Driver Strength Configuration Register (Gpiox_ DS)
132
AFIO Registers
132
AFIO Register Overview
132
Table 5-37 AFIO Register Overview
132
AFIO Configuration Register (AFIO_CFG)
133
AFIO External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1)
134
AFIO External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2)
134
AFIO External Interrupt Configuration Register 3 (AFIO_EXTI_CFG3)
135
AFIO External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4)
136
Interrupts and Events
137
Nested Vectored Interrupt Controller
137
Systick Calibration Value Register
137
Interrupt and Exception Vectors
137
Table 6-1 Vector Table
137
External Interrupt/Event Controller (EXTI)
140
Introduction
140
Main Features
140
Functional Description
141
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram
141
EXTI Line Mapping
143
Figure 6-2 External Interrupt Generic I/O Mapping
143
EXTI Registers
145
EXTI Register Overview
145
Interrupt Mask Register(EXTI_IMASK)
145
Table 6-2 EXTI Register Overview
145
Event Mask Register(EXTI_EMASK)
146
Rising Edge Trigger Selection Register(EXTI_RT_CFG)
146
Falling Edge Trigger Selection Register(EXTI_FT_CFG)
147
Software Interrupt Enable Register(EXTI_SWIE)
147
Interrupt Request Pending Register(EXTI_PEND)
148
RTC Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
149
DMA Controller
150
Introduction
150
Main Features
150
Block Diagram
151
Function Description
151
DMA Operation
151
Figure 7-1 DMA Block Diagram
151
Channel Priority and Arbitration
152
DMA Channels and Number of Transfers
152
Programmable Data Bit Width, Alignment and Endians
152
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
152
Peripheral/Memory Address Incrementation
154
Channel Configuration Procedure
154
Flow Control
155
Table 7-2 Flow Control Table
155
Circular Mode
156
Error Management
156
Interrupt
156
Table 7-3 DMA Interrupt Request
156
DMA Request Mapping
157
Table 7-4 DMA Request Mapping
157
DMA Registers
158
DMA Register Overview
158
Table 7-5 DMA Register Overview
158
DMA Interrupt Status Register (DMA_INTSTS)
159
DMA Interrupt Flag Clear Register (DMA_INTCLR)
159
DMA Channel X Configuration Register (Dma_Chcfgx)
160
DMA Channel X Transfer Number Register (Dma_Txnumx)
162
DMA Channel X Peripheral Address Register (Dma_Paddrx)
162
DMA Channel X Memory Address Register (Dma_Maddrx)
163
DMA Channel X Channel Request Select Register (Dma_Chselx)
163
CRC Calculation Unit
165
CRC Introduction
165
CRC Main Features
165
CRC32 Module
165
CRC16 Module
165
CRC Function Description
166
Crc32
166
Crc16
166
Figure 8-1 CRC Calculation Unit Block Diagram
166
CRC Registers
167
CRC Register Overview
167
CRC32 Data Register (CRC_CRC32DAT)
167
CRC32 Independent Data Register (CRC_CRC32IDAT)
167
Table 8-1 CRC Register Overview
167
CRC32 Control Register (CRC_CRC32CTRL)
168
CRC16 Control Register (CRC_CRC16CTRL)
168
CRC16 Input Data Register (CRC_CRC16DAT)
169
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
169
LRC Result Register (CRC_LRC)
170
Advanced-Control Timers (TIM1 and TIM8)
171
TIM1 and TIM8 Introduction
171
Main Features of TIM1 and TIM8
171
TIM1 and TIM8 Function Description
172
Time-Base Unit
172
Figure 9-1 Block Diagram of TIM1 and TIM8
172
Prescaler Description
173
Counter Mode
173
Figure 9-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
173
Up-Counting Mode
173
Figure 9-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
175
Down-Counting Mode
177
Figure 9-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
177
Center-Aligned Mode
177
Figure 9-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
178
Figure 9-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
179
Counter Underflow
179
Repetition Counter
179
Figure 9-8 Repeat Count Sequence Diagram in Down-Counting Mode
180
Figure 9-9 Repeat Count Sequence Diagram in Up-Counting Mode
181
Figure 9-10 Repeat Count Sequence Diagram in Center-Aligned Mode
181
Clock Selection
182
Figure 9-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
182
Figure 9-12 TI2 External Clock Connection Example
183
Figure 9-13 Control Circuit in External Clock Mode 1
184
Figure 9-14 External Trigger Input Block Diagram
184
Capture/Compare Channels
185
Figure 9-15 Control Circuit in External Clock Mode 2
185
Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
186
Figure 9-17 Capture/Compare Channel 1 Main Circuit
187
Figure 9-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
187
Input Capture Mode
188
Figure 9-19 Output Part of Channelx (X= 4)
188
PWM Input Mode
189
Forced Output Mode
190
Figure 9-20 PWM Input Mode Timing
190
Output Compare Mode
191
PWM Mode
192
PWM Center-Aligned Mode
192
Figure 9-21 Output Compare Mode, Toggle on OC1
192
Figure 9-22 Center-Aligned PWM Waveform (AR=8)
193
Figure 9-23 Edge-Aligned PWM Waveform (APR=8)
194
One-Pulse Mode
195
Figure 9-24 Example of One-Pulse Mode
195
Clearing the Ocxref Signal on an External Event
196
Complementary Outputs with Dead-Time Insertion
197
Figure 9-25 Clearing the Ocxref of Timx
197
Figure 9-26 Complementary Output with Dead-Time Insertion
198
Break Function
199
Debug Mode
201
Timx and External Trigger Synchronization
201
Slave Mode: Reset Mode
201
Figure 9-27 Output Behavior in Response to a Break
201
Slave Mode: Trigger Mode
202
Figure 9-28 Control Circuit in Reset Mode
202
Slave Mode: Gated Mode
203
Figure 9-29 Control Circuit in Trigger Mode
203
Figure 9-30 Control Circuit in Gated Mode
204
Timer Synchronization
205
6-Step PWM Generation
205
Figure 9-31 Control Circuit in Trigger Mode + External Clock Mode2
205
Encoder Interface Mode
206
Figure 9-32 6-Step PWM Generation, COM Example (OSSR=1)
206
Table 9-1 Counting Direction Versus Encoder Signals
207
Figure 9-33 Example of Counter Operation in Encoder Interface Mode
207
Figure 9-34 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
208
Interfacing with Hall Sensor
209
Figure 9-35 Example of Hall Sensor Interface
210
Timx Register Description(X=1, 8)
211
Register Overview
211
Table 9-2 Register Overview
211
Control Register 1 (Timx_Ctrl1)
212
Control Register 2 (Timx_Ctrl2)
214
Slave Mode Control Register (Timx_Smctrl)
216
Table 9-3 Timx Internal Trigger Connection
218
Dma/Interrupt Enable Registers (Timx_Dinten)
219
Status Registers (Timx_Sts)
220
Event Generation Registers (Timx_Evtgen)
222
Capture/Compare Mode Register 1 (Timx_Ccmod1)
223
Capture/Compare Mode Register 2 (Timx_Ccmod2)
227
Capture/Compare Enable Registers (Timx_Ccen)
228
Table 9-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
230
Counters (Timx_Cnt)
231
Prescaler (Timx_Psc)
231
Auto-Reload Register (Timx_Ar)
232
Repeat Count Registers (Timx_Repcnt)
232
Capture/Compare Register 1 (Timx_Ccdat1)
233
Capture/Compare Register 2 (Timx_Ccdat2)
233
Capture/Compare Register 3 (Timx_Ccdat3)
234
Capture/Compare Register 4 (Timx_Ccdat4)
234
Break and Dead-Time Registers (Timx_Bkdt)
235
DMA Control Register (Timx_Dctrl)
237
DMA Transfer Buffer Register (Timx_Daddr)
237
Capture/Compare Mode Registers 3(Timx_Ccmod3)
238
Capture/Compare Register 5 (Timx_Ccdat5)
239
Capture/Compare Register 6 (Timx_Ccdat6)
239
General-Purpose Timers (TIM3)
240
General-Purpose Timers Introduction
240
Main Features of General-Purpose Timers
240
General-Purpose Timers Description
241
Time-Base Unit
241
Figure 10-1 Block Diagram of Timx(X=3
241
Counter Mode
242
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
242
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
243
Figure 9-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
244
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
244
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
245
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
246
Clock Selection
247
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
247
Figure 10-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
248
Figure 10-9 TI2 External Clock Connection Example
249
Figure 10-10 Control Circuit in External Clock Mode 1
250
Figure 10-11 External Trigger Input Block Diagram
250
Capture/Compare Channels
251
Figure 10-12 Control Circuit in External Clock Mode 2
251
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
252
Figure 10-14 Capture/Compare Channel 1 Main Circuit
253
Input Capture Mode
254
Figure 10-15 Output Part of Channelx (X = 1,2,3,4;Take Channel 4 as an Example
254
PWM Input Mode
255
Forced Output Mode
256
Output Compare Mode
256
Figure 10-16 PWM Input Mode Timing
256
PWM Mode
258
Figure 10-17 Output Compare Mode, Toggle on OC1
258
Figure 10-18 Center-Aligned PWM Waveform (AR=8)
259
Figure 10-19 Edge-Aligned PWM Waveform (APR=8)
260
One-Pulse Mode
261
Figure 10-20 Example of One-Pulse Mode
261
Clearing the Ocxref Signal on an External Event
262
Debug Mode
263
Timx and External Trigger Synchronization
263
Timer Synchronization
263
Figure 10-21 Control Circuit in Reset Mode
263
Figure 10-22 Block Diagram of Timer Interconnection
264
Figure 10-23 TIM3 Gated by OC1REF of TIM1
265
Figure 10-24 TIM3 Gated by Enable Signal of TIM1
266
Figure 10-25 Trigger TIM3 with an Update of TIM1
267
Encoder Interface Mode
268
Table 10-1 Counting Direction Versus Encoder Signals
268
Figure 10-26 Triggers Timers 1 and 3 Using the TI1 Input of TIM1
268
Figure 10-27 Example of Counter Operation in Encoder Interface Mode
269
Interfacing with Hall Sensor
270
Timx Register Description(X=3)
270
Register Overview
270
Table 10-2 Register Overview
270
Control Register 1 (Timx_Ctrl1)
272
Control Register 2 (Timx_Ctrl2)
274
Slave Mode Control Register (Timx_Smctrl)
275
Dma/Interrupt Enable Registers (Timx_Dinten)
277
Table 10-3 Timx Internal Trigger Connection
277
Status Registers (Timx_Sts)
278
Event Generation Registers (Timx_Evtgen)
280
Capture/Compare Mode Register 1 (Timx_Ccmod1)
281
Capture/Compare Mode Register 2 (Timx_Ccmod2)
284
Capture/Compare Enable Registers (Timx_Ccen)
286
Counters (Timx_Cnt)
287
Table 10-4 Output Control Bits of Standard Ocx Channel
287
Prescaler (Timx_Psc)
288
Auto-Reload Register (Timx_Ar)
288
Capture/Compare Register 1 (Timx_Ccdat1)
288
Capture/Compare Register 2 (Timx_Ccdat2)
289
Capture/Compare Register 3 (Timx_Ccdat3)
289
Capture/Compare Register 4 (Timx_Ccdat4)
290
DMA Control Register (Timx_Dctrl)
290
DMA Transfer Buffer Register (Timx_Daddr)
291
Basic Timers (TIM6)
293
Basic Timers Introduction
293
Main Features of Basic Timers
293
Basic Timers Description
293
Time-Base Unit
293
Figure 11-1 Block Diagram of Timx(X = 6
293
Counter Mode
294
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
294
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
295
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
296
Clock Selection
297
Debug Mode
297
Timx Register Description(X=6)
297
Figure 11-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
297
Register Overview
298
Control Register 1 (Timx_Ctrl1)
298
Table 11-1 Register Overview
298
Dma/Interrupt Enable Registers (Timx_Dinten)
299
Status Registers (Timx_Sts)
300
Event Generation Registers (Timx_Evtgen)
300
Counters (Timx_Cnt)
301
Prescaler (Timx_Psc)
301
Automatic Reload Register (Timx_Ar)
302
Low Power Timer (LPTIM)
303
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