Nations N32L40 Series Manuals

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Nations N32L40 Series User Manual

Nations N32L40 Series User Manual (679 pages)

32-bit ARM Cortex-M4F microcontroller

Brand: Nations | Category: Microcontrollers | Size: 12 MB

Table of Contents

Table of Contents
2
Abbreviations in the Text
25
Describes the List of Abbreviations Used in the Register Table
25
Available Peripherals
25
Memory and Bus Architecture
26
System Architecture
26
Bus Architecture
26
Figure 2-1 Bus Architecture
26
Bus Address Mapping
27
Table 2-1 List of Peripheral Register Addresses
28
Figure 2-2 Bus Address Map
28
Bit Banding
30
Boot Management
30
Boot Configuration
31
Table 2-2 List of Boot Mode
31
Embedded Boot Loader
32
Memory System
32
FLASH Specification
32
Table 2-3 Flash Bus Address List
33
Option Byte
36
Table 2-4 Option Byte List
37
Write Protect
38
Read Protection
38
Table 2-5 Read Protection Configuration List
39
Table 2-6 Flash Read-Write-Erase (1) Permission Control Table
40
Icache
44
Software Interface
44
Sram
46
FLASH Register Description
46
Table 2-7 FLASH Register Overview
46
Power Control (PWR)
56
General Description
56
Power Supply
56
Power Supply Supervisor
57
Figure 3-1 Power Supply Block Diagram
57
Figure 3-2 Brown-Out Reset (BOR) Waveform
58
Programmable Voltage Detector (PVD)
58
Power Modes
59
Table 3-1 Power Modes
59
Figure 3-3 PVD Threshold Waveform
59
Table 3-2 Blocks Running State
60
RUN Mode
61
SLEEP Mode
62
Enter SLEEP Mode
62
Exit SLEEP Mode
63
LOW POWER RUN Mode
63
LOW POWER SLEEP Mode
64
STOP2 Mode
64
STANDBY Mode
65
Enter STANDBY Mode
65
Exit STANDBY Mode
66
Low-Power Auto-Wakeup (AWU) Mode
66
PWR Registers
67
PWR Register Overview
67
Power Control Register 1 (PWR_CTRL1)
67
Table 3-3 PWR Register Overview
67
Power Control Register 2 (PWR_CTRL2)
68
Power Control Register 3 (PWR_CTRL3)
69
Power Status Register 1 (PWR_STS1)
71
Power Status Register 1 (PWR_STS1)
72
Power Status Clear Register (PWR_STSCLR)
73
Reset and Clock Control (RCC)
74
Reset Control Unit
74
Power Reset
74
System Reset
74
Software Reset
75
Low-Power Management Reset
75
Low Power Domain Reset
75
Clock Control Unit
75
Figure 4-1 System Reset Generation
75
Clock Tree Diagram
77
HSE Clock
77
Figure 4-2 Clock Tree
77
External Crystal/Ceramic Resonator (HSE Crystal)
78
HSI Clock
78
Figure 4-3 HSE/LSE Clock Source
78
MSI Clock
79
PLL Clock
79
LSE Clock
80
LSI Clock
80
Figure 4-4 PLL Clock Source Selection
80
System Clock (SYSCLK) Selection
81
Clock Security System (CLKSS)
81
LSE Clock Security System (LSECSS)
82
RTC Clock
82
Watchdog Clock
82
Clock Output (MCO)
82
RCC Registers
83
RCC Register Overview
83
Table 4-1 RCC Register Overview
83
Clock Control Register (RCC_CTRL)
84
Clock Configuration Register (RCC_CFG)
86
Clock Interrupt Register (RCC_CLKINT)
90
APB2 Peripheral Reset Register (RCC_APB2PRST)
93
APB1 Peripheral Reset Register (RCC_APB1PRST)
94
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
97
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
98
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
99
LOW POWER Domain Control Register (RCC_LDCTRL)
102
Clock Control/Status Register (RCC_CTRLSTS)
103
AHB Peripheral Reset Register (RCC_AHBPRST)
106
Clock Configuration Register 2 (RCC_CFG2)
106
Clock Configuration Register 3 (RCC_CFG3)
108
Retention Domain Control Register (RCC_RDCTRL)
109
PLL and HSI Configuration Register (RCC_PLLHSIPRE)
111
SRAM Control/Status Register (RCC_SRAM_CTRLSTS)
111
GPIO and AFIO
113
Summary
113
I/O Function Description
114
I/O Mode Configuration
114
Table 5-1 I/O Port Configuration Table
114
Figure 5-1 Basic Structure of I/O Port
114
Table 5-2 Input and Output Characteristics of Different Configurations
115
Pull-Up + Pull-Down
115
Figure 5-2 Input Floating/Pull-Up/Pull-Down Configuration
116
Figure 5-3 Output Mode Configuration
117
Analog Mode
118
Figure 5-4 Alternate Function Configuration
118
Status after Reset
119
Individual Bit Setting and Bit Clearing
119
Figure 5-5 High Impedance Analog Mode Configuration
119
External Interrupt/Wake-Up Line
120
JTAG/SWD Alternate Function Remapping
120
Table 5-3 Debug Port Image
121
Table 5-4 ADC External Trigger Injection Conversion Alternate Function Remapping
121
Table 5-5 ADC External Trigger Regular Conversion Alternate Function Remapping
122
Table 5-6 TIM1 Alternate Function Remapping
122
Table 5-7 TIM2 Alternate Function Remapping
122
Table 5-8 TIM3 Alternate Function Remapping
123
Table 5-9 TIM4 Alternate Function Remapping
123
Table 5-10 TIM5 Alternate Function Remapping
123
Table 5-11 TIM8 Alternate Function Remapping
123
Table 5-12 TIM9 Alternate Function Remapping
124
Table 5-13 LPTIM Alternate Function Remapping
124
Table 5-14 CAN Alternate Function Remapping
124
Table 5-15 USART1 Alternate Function Remapping
125
Table 5-16 USART2 Alternate Function Remapping
125
Table 5-17 USART3 Alternate Function Remapping
125
Table 5-18 UART4 Alternate Function Remapping
126
Table 5-19 UART5 Alternate Function Remapping
126
Table 5-20 LPUART Alternate Function Remapping
126
Table 5-21 I2C1 Alternate Function Remapping
127
Table 5-22 I2C2 Alternate Function Remapping
128
Table 5-23 SPI1 Alternate Function Remapping
128
Table 5-24 SPI2/I2S2 Alternate Function Remapping
129
Table 5-25 COMP1 Alternate Function Remapping
129
Table 5-26 COMP2 Alternate Function Remapping
129
Table 5-27 EVENTOUT Alternate Function Remapping
130
Table 5-28 RTC Alternate Function Remapping
130
Table 5-29 LCD Alternate Function Remapping
130
I/O Configuration of Peripherals
131
Table 5-30 LCD Pin Mapping Function Distinction
131
Table 5-31 ADC/DAC
131
Table 5-32 TIM1/TIM8
132
Table 5-33 TIM2/3/4/5/9
132
Table 5-34 LPTIM
132
Table 5-35 CAN
132
Table 5-36 USART
132
Table 5-37 UART
132
Table 5-38 LPUART
133
Table 5-39 I2C
133
Table 5-40 SPI-I2S
133
Table 5-41 USB
133
Table 5-42 JTAG/SWD
133
Table 5-43 Other
133
GPIO Locking Mechanism
134
GPIO Register
134
GPIO Register Overview
134
Table 5-44 GPIO Register Overview
135
GPIO Mode Description Register (Gpiox_Pmode)
136
GPIO Type Definition (Gpiox_Potype)
136
GPIO Port Slew Rate Configuration Register (Gpiox_Sr)
137
GPIO Pull-Up/Pull-Down Description Register (Gpiox_Pupd)
137
GPIO Input Data Register (Gpiox_Pid)
138
GPIO Output Data Register (Gpiox_Pod)
138
GPIO Bit Set/Clear Register (Gpiox_Pbsc)
139
GPIO Configuration Lock Register (Gpiox_Plock)
139
GPIO Alternate Function Low Register (Gpiox_Afl)
140
GPIO Alternate Function High Register (Gpiox_Afh)
141
GPIO Bit Clear Register (Gpiox_Pbc)
142
GPIO Driver Strength Configuration Register (Gpiox_Ds)
142
AFIO Register
143
AFIO Register Overview
143
AFIO Mapping Configuration Control Register (AFIO_RMP_CFG)
143
Table 5-45 AFIO Register Overview
143
AFIO External Interrupt Configuration Register 1(AFIO_EXTI_CFG1)
144
AFIO External Interrupt Configuration Register 2(AFIO_EXTI_CFG2)
145
AFIO External Interrupt Configuration Register 3(AFIO_EXTI_CFG3)
146
AFIO External Interrupt Configuration Register 4(AFIO_EXTI_CFG4)
147
Interrupts and Events
148
Nested Vector Interrupt Register
148
Systick Calibration Value Register
148
Interrupt and Exception Vectors
148
Table 6-1 Vector Table
148
External Interrupt/Event Controller (EXTI)
151
Introduction
151
Main Features
151
Functional Description
152
Figure 6-1 External Interrupt/Event Controller Block Diagram
152
EXTI Line Image
153
Figure 6-2 External Interrupt Generic I/O Image
153
EXTI Registers
154
EXTI Registers Overview
155
EXTI Interrupt Mask Register (EXTI_IMASK)
155
Table 6-2 EXTI Register Overview
155
EXTI Event Mask Register (EXTI_EMASK)
156
EXTI Rising Edge Trigger Configuration Register (EXTI_RT_CFG)
156
EXTI Falling Edge Trigger Configuration Register (EXTI_FT_CFG)
157
EXTI Software Interrupt Event Register (EXTI_SWIE)
157
EXTI Pending Register (EXTI_PEND)
158
EXTI Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
158
DMA Controller
160
Introduction
160
Main Features
160
Block Diagram
161
Function Description
161
DMA Operation
161
Figure 7-1 DMA Block Diagram
161
Channel Priority and Arbitration
162
DMA Channels and Number of Transfers
162
Programmable Data Bit Width, Alignment and Endians
162
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
163
Peripheral/Memory Address Incrementation
164
Channel Configuration Procedure
164
Flow Control
165
Table 7-2 Flow Control Table
165
Circular Mode
166
Error Management
166
Interrupt
166
DMA Request Mapping
166
Table 7-3 DMA Interrupt Request
166
Table 7-4 DMA Request Mapping
167
DMA Registers
168
DMA Register Overview
168
Table 7-5 DMA Register Overview
168
DMA Interrupt Status Register (DMA_INTSTS)
170
DMA Interrupt Flag Clear Register (DMA_INTCLR)
171
DMA Channel X Configuration Register (Dma_Chcfgx)
171
DMA Channel X Transfer Number Register (Dma_Txnumx)
173
DMA Channel X Peripheral Address Register (Dma_Paddrx)
174
DMA Channel X Memory Address Register (Dma_Maddrx)
174
DMA Channel X Channel Request Select Register (Dma_Chselx)
175
CRC Calculation Unit
177
CRC Introduction
177
CRC Main Features
177
CRC32 Module
177
CRC16 Module
177
CRC Function Description
178
Crc32
178
Crc16
178
Figure 8-1 CRC Calculation Unit Block Diagram
178
CRC Registers
179
CRC Register Overview
179
CRC32 Data Register (CRC_CRC32DAT)
179
CRC32 Independent Data Register (CRC_CRC32IDAT)
179
Table 8-1 CRC Register Overview
179
CRC32 Control Register (CRC_CRC32CTRL)
180
CRC16 Control Register (CRC_CRC16CTRL)
180
CRC16 Input Data Register (CRC_CRC16DAT)
181
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
181
LRC Result Register (CRC_LRC)
182
Cryptographic Algorithm Hardware Acceleration Engine (SAC)
183
Advanced-Control Timers (TIM1 and TIM8)
184
TIM1 and TIM8 Introduction
184
Main Features of TIM1 and TIM8
184
TIM1 and TIM8 Function Description
185
Time-Base Unit
185
Figure 10-1 Block Diagram of TIM1 and TIM8
185
Prescaler Description
186
Counter Mode
186
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
186
Up-Counting Mode
186
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
187
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
188
Down-Counting Mode
189
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
189
Center-Aligned Mode
189
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
190
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
191
Counter Underflow
191
Repetition Counter
191
Figure 10-8 Repeat Count Sequence Diagram in Down-Counting Mode
192
Figure 10-9 Repeat Count Sequence Diagram in Up-Counting Mode
193
Figure 10-10 Repeat Count Sequence Diagram in Center-Aligned Mode
193
Clock Selection
194
Figure 10-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
194
Figure 10-12 TI2 External Clock Connection Example
195
Figure 10-13 Control Circuit in External Clock Mode 1
196
Figure 10-14 External Trigger Input Block Diagram
196
Capture/Compare Channels
197
Figure 10-15 Control Circuit in External Clock Mode 2
197
Figure 10-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
198
Figure 10-17 Capture/Compare Channel 1 Main Circuit
199
Input Capture Mode
200
Figure 10-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
200
Figure 10-19 Output Part of Channelx (X= 4)
200
PWM Input Mode
201
Forced Output Mode
202
Figure 10-20 PWM Input Mode Timing
202
Output Compare Mode
203
PWM Mode
204
PWM Center-Aligned Mode
204
Figure 10-21 Output Compare Mode, Toggle on OC1
204
Figure 10-22 Center-Aligned PWM Waveform (AR=8)
205
Figure 10-23 Edge-Aligned PWM Waveform (APR=8)
206
One-Pulse Mode
207
Clearing the Ocxref Signal on an External Event
208
Complementary Outputs with Dead-Time Insertion
209
Figure 10-24 Clearing the Ocxref of Timx
209
Figure 10-25 Complementary Output with Dead-Time Insertion
210
Break Function
211
Figure 10-26 Output Behavior in Response to a Break
213
Debug Mode
213
Timx and External Trigger Synchronization
213
Slave Mode: Reset Mode
213
Slave Mode: Trigger Mode
214
Figure 10-27 Control Circuit in Reset Mode
214
Slave Mode: Gated Mode
215
Figure 10-28 Control Circuit in Trigger Mode
215
Figure 10-29 Control Circuit in Gated Mode
216
Timer Synchronization
217
6-Step PWM Generation
217
Figure 10-30 Control Circuit in Trigger Mode + External Clock Mode2
217
Encoder Interface Mode
218
Figure 10-31 6-Step PWM Generation, COM Example (OSSR=1)
218
Table 10-1 Counting Direction Versus Encoder Signals
219
Figure 10-32 Example of Counter Operation in Encoder Interface Mode
219
Interfacing with Hall Sensor
220
Figure 10-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
220
Advanced-Control
221
Figure 10-34 Example of Hall Sensor Interface
221
Timx Register Description(X=1, 8)
222
Register Overview
222
Table 10-2 Register Overview
222
Control Register 1 (Timx_Ctrl1)
223
Control Register 2 (Timx_Ctrl2)
225
Slave Mode Control Register (Timx_Smctrl)
227
Dma/Interrupt Enable Registers (Timx_Dinten)
229
Table 10-3 Timx Internal Trigger Connection
229
Status Registers (Timx_Sts)
231
Event Generation Registers (Timx_Evtgen)
233
Capture/Compare Mode Register 1 (Timx_Ccmod1)
234
Capture/Compare Mode Register 2 (Timx_Ccmod2)
237
Capture/Compare Enable Registers (Timx_Ccen)
239
Table 10-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
241
Counters (Timx_Cnt)
242
Prescaler (Timx_Psc)
242
Auto-Reload Register (Timx_Ar)
242
Repeat Count Registers (Timx_Repcnt)
242
Capture/Compare Register 1 (Timx_Ccdat1)
243
Capture/Compare Register 2 (Timx_Ccdat2)
243
Capture/Compare Register 3 (Timx_Ccdat3)
244
Capture/Compare Register 4 (Timx_Ccdat4)
244
Break and Dead-Time Registers (Timx_Bkdt)
245
DMA Control Register (Timx_Dctrl)
247
DMA Transfer Buffer Register (Timx_Daddr)
247
Capture/Compare Mode Registers 3(Timx_Ccmod3)
248
Capture/Compare Register 5 (Timx_Ccdat5)
249
Capture/Compare Register 6 (Timx_Ccdat6)
249
General-Purpose Timers (TIM2, TIM3, TIM4, TIM5 and TIM9)
250
General-Purpose Timers Introduction
250
Main Features of General-Purpose Timers
250
General-Purpose Timers Description
251
Time-Base Unit
251
Figure 11-1 Block Diagram of Timx（X=2, 3 ,4 ,5 and 9
251
Counter Mode
252
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
252
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
254
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
255
Figure 11-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
256
Figure 11-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
257
Clock Selection
258
Figure 11-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
258
Figure 11-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
259
Figure 11-9 TI2 External Clock Connection Example
260
Figure 11-10 Control Circuit in External Clock Mode 1
261
Figure 11-11 External Trigger Input Block Diagram
261
Capture/Compare Channels
262
Figure 11-12 Control Circuit in External Clock Mode 2
262
Figure 11-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
263
Figure 11-14 Capture/Compare Channel 1 Main Circuit
264
Input Capture Mode
265
Figure 11-15 Output Part of Channelx （X = 1,2,3,4;Take Channel 4 as an Example
265
PWM Input Mode
266
Forced Output Mode
267
Output Compare Mode
267
Figure 11-16 PWM Input Mode Timing
267
PWM Mode
269
Figure 11-17 Output Compare Mode, Toggle on OC1
269
Figure 11-18 Center-Aligned PWM Waveform (AR=8)
270
Figure 11-19 Edge-Aligned PWM Waveform (APR=8)
271
One-Pulse Mode
272
Figure 11-20 Example of One-Pulse Mode
272
Clearing the Ocxref Signal on an External Event
273
Debug Mode
274
Timx and External Trigger Synchronization
274
Timer Synchronization
274
Figure 11-21 Control Circuit in Reset Mode
274
Figure 11-22 Block Diagram of Timer Interconnection
275
Figure 11-23 TIM2 Gated by OC1REF of TIM1
276
Figure 11-24 TIM2 Gated by Enable Signal of TIM1
277
Figure 11-25 Trigger TIM2 with an Update of TIM1
278
Encoder Interface Mode
279
Figure 11-26 Triggers Timers 1 and 2 Using the TI1 Input of TIM1
279
Table 11-1 Counting Direction Versus Encoder Signals
280
Figure 11-27 Example of Counter Operation in Encoder Interface Mode
280
Interfacing with Hall Sensor
281
Timx Register Description(X=2, 3 ,4 ,5 and 9)
281
Register Overview
281
Table 11-2 Register Overview
281
Figure 11-28 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
281
Control Register 1 (Timx_Ctrl1)
283
Control Register 2 (Timx_Ctrl2)
285
Slave Mode Control Register (Timx_Smctrl)
286
Dma/Interrupt Enable Registers (Timx_Dinten)
288
Table 11-3 Timx Internal Trigger Connection
288
Status Registers (Timx_Sts)
290
Event Generation Registers (Timx_Evtgen)
291
Capture/Compare Mode Register 1 (Timx_Ccmod1)
292
Capture/Compare Mode Register 2 (Timx_Ccmod2)
295
Capture/Compare Enable Registers (Timx_Ccen)
297
Counters (Timx_Cnt)
298
Prescaler (Timx_Psc)
298
Table 11-4 Output Control Bits of Standard Ocx Channel
298
Auto-Reload Register (Timx_Ar)
299
Capture/Compare Register 1 (Timx_Ccdat1)
299
Capture/Compare Register 2 (Timx_Ccdat2)
299
Capture/Compare Register 3 (Timx_Ccdat3)
300
Capture/Compare Register 4 (Timx_Ccdat4)
300
DMA Control Register (Timx_Dctrl)
301
DMA Transfer Buffer Register (Timx_Daddr)
302
Basic Timers (TIM6 and TIM7)
303
Basic Timers Introduction
303
Main Features of Basic Timers
303
Figure 12-1 Block Diagram of Timx（X = 6 and 7
303
Basic Timers Description
304
Time-Base Unit
304
Figure 12-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
304
Counter Mode
305
Figure 12-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
306
Figure 12-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
307
Clock Selection
308
Debug Mode
308
Timx Register Description(X = 6 and 7)
308
Figure 12-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
308
Register Overview
309
Control Register 1 (Timx_Ctrl1)
309
Table 12-1 Register Overview
309
Control Register 2 (Timx_Ctrl2)
310
Dma/Interrupt Enable Registers (Timx_Dinten)
311
Status Registers (Timx_Sts)
311
Event Generation Registers (Timx_Evtgen)
312
Counters (Timx_Cnt)
312
Prescaler (Timx_Psc)
312
Automatic Reload Register (Timx_Ar)
313
Low Power Timer (LPTIM)
314
Introduction
314
Main Features
314
Block Diagram
315
Function Description
315
LPTIM Clocks and On-Off Control
315
Figure 13-1 LPTIM Diagram
315
Prescaler
316
Glitch Filter
316
Table 13-1 Pre-Scaler Division Ratios
316
Timer Enable
317
Trigger Multiplexer
317
Table 13-2 9 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits
317
Figure 13-2 Glitch Filter Timing Diagram
317
Operating Mode
318
Figure 13-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
318
One-Shot Mode
319
Figure 13-4 PTIM Output Waveform, Single Counting Mode Configuration
319
Waveform Generation
320
Figure 13-5 LPTIM Output Waveform, Single Counting Mode Configuration and One-Time Mode Activated
320
Register Update
321
Figure 13-6 Waveform Generation
321
Counter Mode
322
Encoder Mode
323
Table 13-3 Encoder Counting Scenarios
323
Non-Orthogonal Encoder Mode
324
Figure 13-7 Encoder Mode Counting Sequence
324
Timeout Function
325
Figure 13-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally
325
Figure 13-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working
325
LPTIM Interrupts
326
LPTIM Registers
326
LPTIM Register Overview
326
Table 13-4 Interruption Events
326
LPTIM Interrupt and Status Register (LPTIM_INTSTS)
327
LPTIM Interrupt Clear Register (LPTIM_INTCLR)
328
LPTIM Interrupt Enable Register (LPTIM_INTEN)
329
LPTIM Configuration Register (LPTIM_CFG)
330
LPTIM Control Register (LPTIM_CTRL)
333
LPTIM Compare Register (LPTIM_COMP)
334
LPTIM Auto-Reload Register (LPTIM_ARR)
334
LPTIM Counter Register (LPTIM_CNT)
334
Real Time Clock (RTC)
336
Introduction
336
Main Feature
336
Function Description
338
RTC Block Diagram
338
Figure 14-1 RTC Block Diagram
338
GPIO Controlled by RTC
339
RTC Register Write Protection
339
RTC Clock and Prescaler
340
RTC Calendar
340
Calendar Initialization and Configuration
341
Calendar Reading
341
Calibration Clock Output
342
Programmable Alarm
342
Alarm Configuration
342
Alarm Output
343
Periodic Automatic Wakeup
343
Wakeup Timer Configuration
343
Timestamp Function
344
Tamper Detection
344
Daylight Saving Time Configuration
345
RTC Reset
345
RTC Sub-Second Register Shift Operation
345
RTC Digital Clock Precision Calibration
346
RTC Low Power Mode
347
RTC Registers
347
RTC Register Overview
347
Table 14-1 RTC Register Overview
347
RTC Calendar Time Register (RTC_TSH)
349
RTC Calendar Date Register (RTC_DATE)
349
RTC Control Register (RTC_CTRL)
350
RTC Initial Status Register (RTC_INITSTS)
352
RTC Prescaler Register (RTC_PRE)
354
RTC Wakeup Timer Register (RTC_WKUPT)
355
RTC Alarm a Register (RTC_ALARMA)
355
RTC Alarm B Register (RTC_ALARMB)
356
RTC Write Protection Register (RTC_WRP)
357
RTC Sub-Second Register (RTC_SUBS)
358
RTC Shift Control Register (RTC_SCTRL)
358
RTC Timestamp Time Register (RTC_TST)
359
RTC Timestamp Date Register (RTC_TSD)
360
RTC Timestamp Sub-Second Register (RTC_TSSS)
360
RTC Calibration Register (RTC_CALIB)
361
RTC Tamper Configuration Register（Rtc_Tmpcfg
362
RTC Alarm a Sub-Second Register (RTC_ALRMASS)
364
RTC Alarm B Sub-Second Register (RTC_ALRMBSS)
365
RTC Option Register (RTC_OPT)
366
RTC Backup Registers (RTC_BKP(1~20))
366
Independent Watchdog (IWDG)
368
Introduction
368
Main Features
368
Function Description
369
Register Access Protection
369
Figure 15-1 Functional Block Diagram of the Independent Watchdog Module
369
Debugging Mode
370
User Interface
370
Operate Flow
370
Table 15-1 IWDG Counting Maximum and Minimum Reset Time
370
IWDG Configuration Flow
371
IWDG Registers
371
IWDG Register Overview
371
Table 15-2 IWDG Register Overview
371
IWDG Key Register (IWDG_KEY)
372
IWDG Pre-Scaler Register (IWDG_PREDIV)
372
IWDG Reload Register (IWDG_RELV)
373
IWDG Status Register (IWDG_STS)
373
Window Watchdog (WWDG)
375
Introduction
375
Main Features
375
Function Description
375
Figure 16-1 Watchdog Block Diagram
375
Timing for Refresh Watchdog and Interrupt Generation
376
Figure 16-2 Refresh Window and Interrupt Timing of WWDG
376
Debug Mode
377
User Interface
377
WWDG Configuration Flow
377
Table 16-1 Maximum and Minimum Counting Time of WWDG
377
WWDG Registers
378
WWDG Register Overview
378
WWDG Control Register (WWDG_CTRL)
378
WWDG Config Register (WWDG_CFG)
378
Table 16-2 WWDG Register Overview
378
WWDG Status Register (WWDG_STS)
379
Analog to Digital Conversion (ADC)
380
Introduction
380
Main Features
380
Function Description
381
ADC Clock
382
Table 17-1 ADC Pins
382
Figure 17-1 Block Diagram of a Single ADC
382
ADC Switch Control
383
Figure 17-2 ADC Clock
383
Channel Selection
384
Figure 17-3 ADC Channels and Pin Connections
385
Internal Channel
386
Single Conversion Mode
386
Continuous Conversion Mode
386
Timing Diagram
386
Analog Watchdog
387
Table 17-2 Analog Watchdog Channel Selection
387
Figure 17-4 Timing Diagram
387
Scanning Mode
388
Injection Channel Management
388
Discontinuous Mode
389
Figure 17-5 Injection Conversion Delay
389
Calibration
390
Data Aligned
390
Figure 17-6 Calibration Sequence Diagram
390
Programmable Channel Sampling Time
391
Externally Triggered Conversion
391
Table 17-3 Right-Align Data
391
Table 17-4 Left-Aligne Data
391
DMA Requests
392
Temperature Sensor
392
Table 17-5 ADC Is Used for External Triggering of Regular Channels
392
Table 17-6 ADC Is Used for External Triggering of Injection Channels
392
Temperature Sensor Using Flow
393
Figure 17-7 Temperature Sensor and VREFINT Diagram of the Channel
393
ADC Interrupt
394
ADC Registers
394
ADC Register Overview
394
Table 17-7 ADC Interrupt
394
Table 17-8 ADC Register Overview
394
ADC Status Register (ADC_STS)
395
ADC Control Register 1 (ADC_CTRL1)
397
ADC Control Register 2 (ADC_CTRL2)
399
ADC Sampling Time Register 1 (ADC_SAMPT1)
401
ADC Sampling Time Register 2 (ADC_ SAMPT2)
401
ADC Injected Channel Data Offset Register X (Adc_Joffsetx)(X=1
402
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
402
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
403
ADC Regular Sequence Register 1 (ADC_RSEQ1)
403
ADC Regular Sequence Register 2 (ADC_RSEQ2)
404
ADC Regular Sequence Register 3 (ADC_RSEQ3)
404
ADC Injection Sequence Register (ADC_JSEQ)
405
ADC Injection Data Register X (Adc_Jdatx) (X= 1
405
ADC Regulars Data Register (ADC_DAT)
406
ADC Differential Mode Selection Register (ADC_DIFSEL)
406
ADC Calibration Factor (ADC_CALFACT)
407
ADC Control Register 3 (ADC_CTRL3)
407
ADC Sampling Time Register 3 (ADC_SAMPT3)
409
Digital to Analog Conversion (DAC)
410
Introduction
410
Main Features
410
DMA Support
410
Table 18-1 DAC Pins
411
Figure 18-1 Block Diagram of a DAC Channel
411
DAC Function Description and Operation Description
412
DAC Enable
412
DAC Output Buffer
412
DAC Data Format
412
DAC Trigger
413
Table 18-2 DAC External Trigger
413
Figure 18-2 Data Register of Single DAC Channel Mode
413
DAC Conversion
414
DAC Output Voltage
414
DMA Requests
414
Figure 18-3 Time Diagram of Transitions with Trigger Disable
414
The Noise
415
Figure 18-4 LFSR Algorithm for DAC
415
Triangular Wave Generation
416
Figure 18-5 DAC Conversion with LFSR Waveform Generation (Enable Software Trigger)
416
DAC Register
417
DAC Registers Overview
417
Table 18-3 DAC Registers Overview
417
Figure 18-6 Triangle Wave Generation of DAC
417
Figure 18-7 DAC Conversion with Trigonometry Generation (Enable Software Trigger)
417
DAC Control Register (DAC_CTRL)
418
DAC Software Trigger Register (DAC_SOTTR)
419
Bit Right Aligned Data Hold Register for DAC (DAC_DR12CH)
420
Bit Left Aligned Data Hold Register for DAC (DAC_DL12CH)
420
8-Bit Right-Aligned Data Hold Register for DAC (DAC_DR8CH)
420
DAC Data Output Register (DAC_DATO)
421
Comparator (COMP)
422
COMP System Connection Block Diagram
422
Figure 19-1 Comparator Controller Functional Diagram
422
COMP Features
423
COMP Configuration Process
423
COMP Working Mode
424
Window Mode
424
Independent Comparator
424
Comparator Interconnection
424
Interrupt
425
COMP Register
426
COMP Register Overview
426
Table 19-1 COMP Register Overview
426
COMP Interrupt Enable Register (COMP_INTEN)
427
COMP Low Power Select Register (COMP_LPCKSEL)
427
COMP Window Mode Register (COMP_WINMODE)
428
COMP Lock Register (COMP_LOCK)
428
COMP Control Register (COMP1_CTRL)
429
COMP Filter Register (COMP1_FILC)
431
COMP Filter Frequency Division Register (COMP1_FILP)
431
COMP Control Register (COMP2_CTRL)
432
COMP Filter Register (COMP2_FILC)
433
COMP Filter Frequency Division Register (COMP2_FILP)
434
COMP Output Select Register (COMP2_OSEL)
434
COMP Reference Voltage Register (COMP_VREFSCL)
435
COMP Test Register(COMP_TEST)
435
COMP Interrupt Status Register (COMP_INTSTS)
436
Operational Amplifier (OPAMP)
437
Main Features
437
OPAMP Function Description
437
OPAMP Working Mode
438
OPAMP Independent Op Amp Mode
438
Figure 20-1 Block Diagram of OPAMP1 and OPAMP2 Connection Diagram
438
OPAMP Follow Mode
439
Figure 20-2 OPAMP Independent Op Amp Mode
439
OPAMP Internal Gain (PGA) Mode
440
Figure 20-3 Follow Mode
440
OPAMP with Filtered Internal Gain Mode
441
Figure 20-4 Internal Gain Mode
441
Figure 20-5 Internal Gain Mode with Filtering
441
OPAMP Calibration
442
OPAMP Independent Write Protection
442
OPAMP TIMER Controls the Switching Mode
442
OPAMP Register
442
OPAMP Register Overview
442
Table 20-1 OPAMP Register Overview
442
OPAMP Control Status Register (OPAMP1_CS)
443
OPAMP Control Status Register (OPAMP2_CS)
444
OPAMP Lock Register (OPAMP_LOCK)
446
Liquid Crystal Display Controller (LCD)
447
Introduction
447
Main Features
447
Functional Block Diagram
448
Figure 21-1 LCD Controller Block Diagram
448
Functional Description
449
Frequency Generator
449
Table 21-1 Frame Rate Calculation Example
449
Common End Driver
450
COM Signal Bias
450
Figure 21-2 Odd-Even Frames Example(1/4 Duty Cycle, 1/3 Bias)
451
Segment Driver
452
Figure 21-3 Static Duty Cycle Example
452
Figure 21-4 1/2 Duty Cycle, 1/2 Bias
453
Figure 21-5 1/3 Duty Cycle, 1/3 Bias
454
Figure 21-6 1/4 Duty Cycle, 1/3 Bias
455
Blink Function
456
Figure 21-7 1/8 Duty Cycle, 1/4 Bias
456
Voltage Generator and Contrast Control
457
Table 21-2 Blink Frequency Configure Example
457
Figure 21-8 LCD Drive Voltage Control
458
Double Buffer Display
459
COM and SEG Multiplexing
459
Figure 21-9 Dead Time
459
Table 21-3 COM and SEG Pins Mapping Table
460
Working Process
464
Low Power Mode
464
Interrupt Request
464
LCD Controller Register
464
LCD Controller Register Overview
465
Table 21-4 LCD Controller Overview
465
LCD Control Register (LCD_CTRL)
466
LCD Frame Control Register (LCD_FCTRL)
467
LCD Status Register (LCD_STS)
469
LCD Clear Register (LCD_CLR)
470
LCD Display Memory Register (Lcd_Ram1_Comx X = 0
471
LCD Display Memory Register (Lcd_Ram2_Comx X = 0
471
LCD Display Memory Register (Lcd_Ram2_Comx X = 4
472
C Interface
473
Introduction
473
Main Features
473
Function Description
473
SDA and SCL Line Control
474
Software Communication Process
474
Start and Stop Conditions
475
Figure 22-1 I 2 C Functional Block Diagram
475
Figure 22-2 I2C Bus Protocol
475
Clock Synchronization and Arbitration
475
Clock Synchronization
476
Figure 22-3 Slave Transmitter Transfer Sequence Diagram
478
Figure 22-4 Slave Receiver Transfer Sequence Diagram
479
Figure 22-5 Master Transmitter Transfer Sequence Diagram
481
Figure 22-6 Master Receiver Transfer Sequence Diagram
483
Error Conditions Description
484
DMA Application
485
Transmit Process
485
Receive Process
485
Packet Error Check
486
Smbus
487
Device Identification
487
Table 22-1 Comparison between Smbus and I2C
487
Bus Protocol
488
Address Resolution Protocol
488
Debug Mode
489
Interrupt Request
489
Table 22-2 I 2 C Interrupt Request
489
I2C Register Description
490
I2C Register Overview
490
Table 22-3 I2C Register Overview
490
I2C Control Register 1 (I2C_CTRL1)
491
I2C Control Register 2 (I2C_CTRL2)
493
I2C Own Address Register 1 (I2C_OADDR1)
494
I2C Own Address Register 2 (I2C_OADDR2)
495
I2C Data Register (I2C_DAT)
495
I2C Status Register 1 (I2C_STS1)
496
I2C Status Register 2 (I2C_STS2)
499
I2C Clock Control Register (I2C_CLKCTRL)
500
I2C Rise Time Register (I2C_TMRISE)
501
Universal Synchronous Asynchronous Receiver Transmitter (USART)
503
Introduction
503
Main Features
503
Functional Block Diagram
504
Function Description
504
Figure 23-1 USART Block Diagram
504
USART Frame Format
505
Figure 23-2 Word Length = 8 Setting
505
Transmitter
506
Table 23-1 Stop Bit Configuration
506
Figure 23-3 Word Length = 9 Setting
506
Figure 23-4 Configuration Stop Bit
507
Single Byte Communication
508
Receiver
508
Start Bit Detection
508
Figure 23-5 TXC/TXDE Changes During Transmission
508
Figure 23-6 Start Bit Detection
509
Framing Error
510
Overrun Error
511
Table 23-2 Data Sampling for Noise Detection
511
Generation of Fractional Baud Rate
511
Table 23-3 Error Calculation When Setting Baud Rate
512
Receiver's Tolerance Clock Deviation
513
Parity Control
513
Even Parity
513
Odd Parity
513
Table 23-4 When Div_Decimal = 0. Tolerance of USART Receiver
513
Table 23-5 When Div_Decimal != 0. Tolerance of USART Receiver
513
Table 23-6 Frame Format
513
DMA Application
514
Figure 23-7 Transmission Using DMA
515
Hardware Flow Control
516
Figure 23-8 Reception Using DMA
516
Figure 23-9 Hardware Flow Control between Two USART
516
Figure 23-10 RTS Flow Control
517
Figure 23-11 CTS Flow Controls
518
Multiprocessor Communication
518
Idle Line Detection
518
Figure 23-12 Mute Mode Using Idle Line Detection
519
Synchronous Mode
520
Figure 23-13 Mute Mode Detected Using Address Mark
520
Figure 23-14 USART Synchronous Transmission Example
521
Figure 23-15 USART Data Clock Timing Example (WL=0)
521
Single-Wire Half-Duplex Mode
522
Figure 23-16 USART Data Clock Timing Example (WL=1)
522
Figure 23-17 RX Data Sampling / Holding Time
522
Irda SIR ENDEC Mode
523
LIN Mode
524
Figure 23-18 Irdasirendec-Block Diagram
524
Figure 23-19 Irda Data Modulation (3/16)-Normal Mode
524
Figure 23-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
526
Smartcard Mode (ISO7816)
527
Figure 23-21 Break Detection and Framing Error Detection in LIN Mode
527
Figure 23-22 ISO7816-3 Asynchronous Protocol
528
Interrupt Request
529
Table 23-7 USART Interrupt Request
529
Figure 23-23 Use 1.5 Stop Bits to Detect Parity Errors
529
Mode Support
530
USART Register
530
USART Register Overview
530
Table 23-8 USART Mode Setting
530
Table 23-9 USART Register Overview
530
USART Status Register (USART_STS)
531
USART Data Register (USART_DAT)
533
USART Baud Rate Register (USART_BRCF)
534
USART Control Register 1 Register (USART_CTRL1)
534
USART Control Register 2 Register (USART_CTRL2)
536
USART Control Register 3 Register (USART_CTRL3)
537
USART Guard Time and Prescaler Register (USART_GTP)
539
Low Power Universal Asynchronous Receiver Transmitter (LPUART)
541
Introduction
541
Main Features
541
Functional Block Diagram
542
Function Description
542
Figure 24-1 LPUART Block Diagram
542
LPUART Frame Format
543
Transmitter
543
Figure 24-2 Frame Format
543
Receiver
545
Figure 24-3 TXC Changes During Transmission
545
Fractional Baud Rate Generation
547
Table 24-1 Data Sampling for Noise Detection
547
Figure 24-4 Data Sampling for Noise Detection
547
Parity Control
548
DMA Application
549
Table 24-2 Parity Frame Format
549
Figure 24-5 Sending Using DMA
550
Hardware Flow Control
551
Figure 24-6 Receiving with DMA
551
Figure 24-7 Hardware Flow Control between Two LPUART
551
Figure 24-8 RTS Flow Control
552
Figure 24-9 CTS Flow Control
552
Low Power Wake up
553
Interrupt Request
553
LPUART Registers
553
LPUART Register Overview
553
Table 24-3 LPUART Interrupt Requests
553
Table 24-4 LPUART Register Overview
553
LPUART Status Register (LPUART_STS)
554
LPUART Interrupt Enable Register (LPUART_INTEN)
555
LPUART Control Register (LPUART_CTRL)
556
LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1)
557
LPUART Data Register (LPUART_DAT)
557
LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2)
558
LPUART Wake up Data Register (LPUART_WUDAT)
558
Serial Peripheral Interface/Inter-IC Sound (SPI/I S)
560
Introduction
560
Main Features
560
SPI Features
560
I 2 S Features
560
SPI Function Description
561
General Description
561
Figure 25-1 SPI Block Diagram
561
Figure 25-2 Selective Management of Hardware/Software
562
Figure 25-3 Master and Slave Applications
563
Data Format
564
SPI Work Mode
564
Figure 25-4 Data Clock Timing Diagram
564
Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full Duplex Mode
565
Figure 25-6 Schematic Diagram of TE/BUSY Change When Host Transmits Continuously in One-Way Only Mode
566
Figure 25-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode (BIDIRMODE = 0 and RONLY = 1)
567
Figure 25-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in Full
567
Duplex Mode
567
Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit-Only Mode
568
Status Flag
570
Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted Discontinuously
570
Disabling the SPI
571
SPI Communication Using DMA
572
CRC Calculation
573
Figure 25-11 Transmission Using DMA
573
Figure 25-12 Reception Using DMA
573
Error Flag
574
SPI Interrupt
575
Table 25-1 SPI Interrupt Request
575
I 2 S Function Description
576
Figure 25-13 I 2 S Block Diagram
576
Supported Audio Protocols
577
Figure 25-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
578
Figure 25-15 I S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
578
Figure 25-16 I 2 S Philips Protocol Standard Waveform (16-Bit Extended to 32-Bit Packet Frame, CLKPOL = 0)
579
Figure 25-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
580
Figure 25-18 MSB Aligns 24-Bit Data, CLKPOL = 0
580
Figure 25-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
581
Figure 25-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
581
Figure 25-21 LSB Aligns 24-Bit Data, CLKPOL = 0
582
Figure 25-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
582
Figure 25-23 PCM Standard Waveform (16 Bits)
583
Figure 25-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
583
Clock Generator
584
Figure 25-25 I 2 S Clock Generator Structure
584
Figure 25-26 Audio Sampling Frequency Definition
584
I 2 S Transmission and Reception Sequence
585
Table 25-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency
585
Status Flag
587
Error Flag
588
I 2 S Interrupt
588
DMA Function
589
SPI and I S Register Description
589
SPI Register Overview
589
Table 25-3 I 2 S Interrupt Request
589
Table 25-4 SPI Register Overview
589
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
590
SPI Control Register 2 (SPI_CTRL2)
592
SPI Status Register (SPI_STS)
593
SPI Data Register (SPI_DAT)
594
SPI CRC Polynomial Register (SPI_CRCPOLY) (Not Used in I S Mode)
594
SPI RX CRC Register (SPI_CRCRDAT) (Not Used in I S Mode)
595
SPI TX CRC Register（Spi_ CRCTDAT
595
SPI_I 2 S Configuration Register（Spi_I2Scfg
596
SPI_I2S Prescaler Register (SPI_I2SPREDIV)
597
Controller Area Network (CAN)
599
Introduction to CAN
599
Main Features of CAN
599
CAN Overall Introduction
599
CAN Module
600
CAN Working Mode
600
Figure 26-1 Topology of CAN Network
600
Normal Mode
601
Initialization Mode
601
Sleep Mode (Low Power)
601
Send Mailbox
602
Receiving Filter
602
Receive FIFO
602
Figure 26-2 CAN Working Mode
602
CAN Test Mode
603
Loopback Mode
603
Figure 26-3 Single CAN Block Diagram
603
Figure 26-4 Loopback Mode
604
Figure 26-5 Silent Mode
605
Figure 26-6 Loopback Silent Mode
605
CAN Debugging Mode
606
CAN Function Description
606
Send Processing
606
Send Priority
606
Cancel Sending
607
Time Triggered Communication Mode
607
Non-Automatic Retransmission Mode
607
Receiving Management
608
Figure 26-7 Send Mailbox Status
608
Figure 26-8 Receive FIFO Status
609
Identifier Filtering
610
Mask Mode
611
Figure 26-9 Filter Bit Width Setting-Register Organization
611
Identifier List Mode
612
Table 26-1 Examples of Filter Numbers
612
Message Storage
613
Table 26-2 Send Mailbox Register List
613
Figure 26-10 Examples of Filter Mechanisms
613
Bit Time Characteristic
614
Table 26-3 Receive Mailbox Register List
614
Figure 26-11 Bit Sequence
615
Figure 26-12 Various CAN Frames
616
CAN Interrupt
617
Figure 26-13 Event Flag and Interrupt Generation
617
Error Management
618
Bus-Off Recovery
618
Figure 26-14 CAN Error State Diagram
618
CAN Configuration Flow
619
CAN Register File
620
Register Description
620
CAN Register Address Overview
621
Table 26-4 CAN Register Overview
621
CAN Control and Status Register
624
CAN Mailbox Register
635
CAN Filter Register
640
Universal Serial Bus Full-Speed Device Interface (Usb_Fs_Device)
644
Introduction
644
Main Features
644
Clock Configuration
645
Functional Description
645
Figure 27-1 USB Device Block Diagram
645
Access Packet Buffer Memory
646
Buffer Description Table
647
Figure 27-2 the User Applications on the Microcontrollers and the USB Modules Access Packet Buffer Memory
647
Double-Buffered Endpoints
648
Figure 27-3 the Relationship between the Buffer Description Table and the Endpoint Packet Buffer
648
Table 27-1 DATTOG and SW_BUF Definitions
649
Table 27-2 How to Use Double Buffering
649
Figure 27-4 Double Buffered Bulk Endpoint Example
650
USB Transfer
651
Control Transfer
652
Figure 27-5 Control Transfer
654
USB Events and Interrupts
655
Table 27-3 How to Use Isochronous Double Buffering
655
Table 27-4 Resume Event Detection
656
USB Interrupt
657
Endpoint Initialization
657
USB Registers
657
USB Register Overview
658
Table 27-5 USB Register Overview
658
USB Endpoint N Register (Usb_Epn), N=[0
659
Table 27-6 Receive Status Code
661
Table 27-7 Send Status Code
661
USB Control Register (USB_CTRL)
662
USB Interrupt Status Register (USB_STS)
663
USB Frame Number Register (USB_FN)
666
USB Device Address Register (USB_ADDR)
666
USB Packet Buffer Description Table Address Register (USB_BUFTAB)
667
Buffer Description Table
667
Send Buffer Address Register N (Usb_Addrn_Tx)
668
Send Data Byte Number Register N (Usb_Cntn_Tx)
668
Receive Buffer Address Register N (Usb_Addrn_Rx)
668
Receive Data Byte Number Register N (Usb_Cntn_Rx)
669
Table 27-8 Endpoint Packet Receive Buffer Size Definition
669
Debug Support (DBG)
671
Overview
671
Figure 28-1 N32L40X Level and Cortex
671
TM -M4F Level Debugging Block Diagram
671
JTAG/SWD Function
672
Switch JTAG/SWD Interface
672
Pin Allocation
672
MCU Debug Function
673
Low-Power Mode Debug Support
673
Table 28-1 Debug Port Pin
673
Peripherals Debug Support
674
DBG Registers
674
DBG Register Overview
674
ID Register (DBG_ID)
674
Table 28-2 DBG Register Overview
674
Debug Control Register (DBG_CTRL)
675
Unique Device Serial Number (UID)
677
Introduction
677
UID Register
677
UCID Register
677
30 Version History
678
31 Notice
679

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