Event Generation Registers (Timx_Evtgen) - Nations N32G43 Series User Manual

Bit field Name
0 UDITF

Event generation registers (TIMx_EVTGEN)

Offset address: 0x14
Reset values: 0x0000
Bit field Name
15：8 Reserved
7 BGN
6 TGN
5 CCUDGN
Description
This bit is set by hardware when the capture event occurs. This bit is cleared by software or by
reading TIMx_CCDAT1.
0: No input capture occurred.
1: Input capture occurred. Counter value has captured in the TIMx_CCDAT1. An edge with
the same polarity as selected has been detected on IC1.
Update interrupt flag
This bit is set by hardware when an update event occurs under the following conditions:
–
When TIMx_CTRL1.UPDIS = 0, and repeat counter value overflow or underflow (An
update event is generated when the repeat counter equals 0).
–
When TIMx_CTRL1.UPRS = 0, TIMx_CTRL1.UPDIS = 0, and set the
TIMx_EVTGEN.UDGN bit by software to reinitialize the CNT.
–
When TIMx_CTRL1.UPRS = 0, TIMx_CTRL1.UPDIS = 0, and the counter CNT is
reinitialized by the trigger event. (See TIMx_SMCTRL Register description)
This bit is cleared by software.
0: No update event occurred
1: Update interrupt occurred
Description
Reserved, the reset value must be maintained
Break generation
This bit can generate a brake event when set by software. And at this time
TIMx_BKDT.MOEN = 0, TIMx_STS.BITF = 1, if the corresponding interrupt and DMA are
enabled, the corresponding interrupt and DMA will be generated. This bit is automatically
cleared by hardware.
0: No action
1: Generated a break event
Trigger generation
This bit can generate a trigger event when set by software. And at this time TIMx_STS.TITF
= 1, if the corresponding interrupt and DMA are enabled, the corresponding interrupt and
DMA will be generated. This bit is automatically cleared by hardware.
0: No action
1: Generated a trigger event
Capture/Compare control update generation
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