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VDDA
VSSA
VDD
VSS
Power supply supervisor
Power on reset (POR) and brown out reset (BOR)
Power-on reset (POR) and brown-out reset (BOR) circuits are integrated inside the chip. BOR is active in all power
modes and cannot be disabled. Five BOR thresholds can be selected via the option byte.
During power-on, the BOR will hold the chip in reset until the supply voltage (V
When V
falls below the selected threshold, the chip will be reset. For more information on switching power supply
DD
reset thresholds, see the Electrical Characteristics section of the relevant data sheet.
Figure 3-1 Power supply block diagram
DAC, ADC, COMP, OPA
USB PHY
Afe_main
TS
HSE,HSI,PLL
OSC300M
TRNG
IO rings (except
PC13/14/15/NRST
PC13/14/15/NRST
Afe_lp
MR/LPR
WKUP
BG/IBIAS/BOR_PVD
MSI/LSI/LSE
Digital peripherals
VDDD
Main Domain
VDDDLP_RET
LPUART
SRAM1(24KB)
COMP digital circuit
Retention Domain
VDDDLP
SRAM2(8KB)
LP domain
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Nations Technologies Inc.
Tel：+86-755-86309900
Email：info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Core
Flash
LPTIM
PWR
RTC
IWDG
) reaches the specified threshold.
DD
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