Event Generation Registers (Timx_Evtgen); Counters (Timx_Cnt); Prescaler (Timx_Psc) - Nations N32G43 Series User Manual

Bit field Name
15:1 Reserved
0 UDITF

Event Generation registers (TIMx_EVTGEN)

Offset address: 0x14
Reset values: 0 x0000
Bit field Name
15：1 Reserved
0 UDGN

Counters (TIMx_CNT)

Offset address: 0x24
Reset value: 0x0000
Bit field Name
15:0 CNT[15:0]

Prescaler (TIMx_PSC)

Offset address: 0x28
Description
Reserved, the reset value must be maintained
Update interrupt flag
This bit is set by hardware when an update event occurs under the following conditions:
–
When TIMx_CTRL1.UPDIS = 0, and counter value overflow.
–
When TIMx_CTRL1.UPRS = 0, TIMx_CTRL1.UPDIS = 0, and set the
TIMx_EVTGEN.UDGN bit by software to reinitialize the CNT.
This bit is cleared by software.
0: No update event occurred
1: Update interrupt occurred
Description
Reserved, the reset value must be maintained.
UDGN: Update generation
Software can set this bit to update configuration register value and hardware will clear it
automatically.
0: No effect.
1: Timer counter will restart and all shadow register will be updated. It will restart prescaler
counter also.
Description
Counter value
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