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Nations N32G003 Series Manuals
Manuals and User Guides for Nations N32G003 Series. We have
1
Nations N32G003 Series manual available for free PDF download: User Manual
Nations N32G003 Series User Manual (319 pages)
32-bit ARM Cortex-M0 microcontroller
Brand:
Nations
| Category:
Microcontrollers
| Size: 6 MB
Table of Contents
Table of Contents
2
Abbreviations in the Text
18
List of Abbreviations for Registers
18
Available Peripherals
18
Memory and Bus Architecture
19
System Architecture
19
Bus Architecture
19
Bus Address Mapping
20
Figure 2-1 Bus Architecture
20
Table 2-1 List of Peripheral Register Addresses
21
Figure 2-2 Bus Address Map
21
Boot Management
22
Memory System
22
FLASH Specification
22
Table 2-2 Flash Bus Address List
23
Option Byte
26
Table 2-3 Option Byte List
27
Table 2-4 Read Protection Configuration List
28
Table 2-5 Flash Read-Write-Erase Permission Control Table
29
Sram
30
FLASH Register Description
31
Table 2-6 FLASH Register Overview
31
Power Control (PWR)
39
General Description
39
Power Supply
39
Figure 3-1 Power Supply Diagram
40
Power Supply Supervisor
40
Power on Reset (POR) / Power down Reset (PDR)
40
Figure 3-2 Power on Reset (POR) / Power down Reset (PDR) Waveform
41
Programmable Voltage Detector (PVD)
41
Low Voltage Reset (LVR)
41
Figure 3-3 PVD Threshold Diagram
41
Power Modes
42
Table 3-1 Power Modes
42
Figure 3-4 LVR Threshold Diagram
42
Table 3-2 Peripheral Running Status
43
STOP Mode
44
PD Mode
44
Debug Mode
45
Low Power Mode Debug Mode Support
45
Peripheral Debug Support
45
PWR Registers
45
PWR Register Overview
45
Table 3-3 PWR Register Overview
45
Power Control Register (PWR_CTRL)
46
Power Control Status Register (PWR_CTRLSTS)
48
Power Control Register 2 (PWR_CTRL2)
49
Power Control Register 3 (PWR_CTRL3)
50
Power Control Register 4 (PWR_CTRL4)
51
Power Control Register 5 (PWR_CTRL5)
52
Power Control Register 6 (PWR_CTRL6)
52
Debug Control Register (DBG_CTRL)
53
Reset and Clock Control (RCC)
55
Reset Control Unit
55
Power Reset
55
System Reset
55
Low-Power Management Reset
56
Figure 4-1 System Reset Generation
56
Clock Control Unit
57
Clock Tree Diagram
58
HSI Clock
58
Figure 4-2 Clock Tree
58
LSI Clock
59
System Clock (SYSCLK) Selection
59
Watchdog Clock
59
TIM6 Clock
60
Clock Output(MCO)
60
RCC Registers
60
RCC Register Overview
60
Table 4-1 RCC Register Overview
60
HSI Clock Control Register (RCC_HSICTRL)
61
Clock Configuration Register (RCC_CFG)
62
Peripheral Reset Register (RCC_PRST)
63
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
65
APB Peripheral Clock Enable Register (RCC_APBPCLKEN)
66
Low Speed Clock Control Register (RCC_LSICTRL)
67
Control/Status Register (RCC_CTRLSTS)
68
Clock Configuration Register 2 (RCC_CFG2)
70
EMC Control Register (RCC_EMCCTRL)
71
GPIO and AFIO
72
Summary
72
IO Function Description
73
IO Mode Configuration
73
Table 5-1 Relationship between I/O Modes and Configurations
73
Figure 5-1 Basic Structure of an I/O Port
73
Table 5-2 I/O List of Functional Features of the Lipin
74
Figure 5-2 Input Mode
75
Figure 5-3 Output Mode
76
Figure 5-4 Alternate Function Mode
77
Figure 5-5 Analog Mode Configuration with High Impedance
77
Status after Reset
78
Individual Bit Setting and Bit Clearing
78
External Interrupt/Wake-Up Line
78
Table 5-3 Correspondence between EXTI Line and Pin
78
Alternate Function
79
Table 5-4 I/O List of Functional Features of the Pin
79
Table 5-5 TIM1 Alternate Function I/O Remapping
79
Table 5-6 TIM3 Alternate Function I/O Remapping
80
Table 5-7 UART1 Alternate Function I/O Remapping
81
Table 5-8 UART2 Alternate Function I/O Remapping
81
Table 5-9 I2C Alternate Function I/O Remapping
82
Table 5-10 SPI Alternate Function I/O Remapping
82
Table 5-11 COMP Alternate Function I/O Remapping
82
Table 5-12 BEEPER Alternate Function I/O Remapping
82
Table 5-13 EVENTOUT Alternate Function I/O Remapping
82
I/O Configuration of Peripherals
83
Table 5-14 MCO Alternate Function I/O Remapping
83
Table 5-15 ADC
83
Table 5-16 TIM1
83
Table 5-17 TIM3
83
Table 5-18 UART
83
Table 5-19 I2C
83
Table 5-20 SPI
83
GPIO Locking Mechanism
84
Table 5-21 COMP
84
Table 5-22 BEEPER
84
Table 5-23 Other
84
GPIO Registers
85
GPIOA Register Overview
85
Table 5-24 GPIOA Register Overview
85
GPIOB Register Overview
87
Table 5-25 GPIOB Register Overview
87
GPIO Port Mode Register (Gpiox_Pmode)
88
GPIO Port Type Register (Gpiox_Potype)
89
GPIO Slew Rate Register (Gpiox_Sr)
89
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupd)
90
GPIO Port Input Data Register (Gpiox_Pid)
91
GPIO Port Output Data Register (Gpiox_Pod)
91
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)
92
GPIO Port Bit Clear Register (Gpiox_Pbc)
92
GPIO Port Lock Register (Gpiox_Plock)
93
GPIO Alternate Function Low Register (Gpiox_Afl)
94
GPIO Alternate Function High Register (Gpiox_Afh)
94
GPIO Driver Strength Register (Gpiox_Ds)
95
AFIO Registers
96
AFIO Register Overview
96
AFIO Configuration Register (AFIO_CFG)
96
Table 5-26 AFIO Register Overview
96
Interrupts and Events
98
Nested Vectored Interrupt Controller
98
Systick Calibration Value Register
98
Interrupt and Exception Vectors
98
Table 6-1 Vector Table
98
External Interrupt/Event Controller (EXTI)
99
Introduction
99
Main Features
99
Functional Description
100
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram
100
EXTI Line Mapping
101
EXTI Registers
102
EXTI Register Overview
102
Interrupt Mask Register(EXTI_IMASK)
102
Table 6-2 EXTI Register Overview
102
Event Mask Register(EXTI_EMASK)
103
Rising Edge Trigger Selection Register(EXTI_RT_CFG)
103
Falling Edge Trigger Selection Register(EXTI_FT_CFG)
103
Software Interrupt Enable Register(EXTI_SWIE)
104
Interrupt Request Pending Register(EXTI_PEND)
104
CRC Calculation Unit
106
CRC Introduction
106
CRC Main Features
106
CRC Function Description
106
Figure 7-1 CRC Calculation Unit Block Diagram
106
CRC Software Calculation Method
107
CRC Registers
107
CRC Register Overview
107
CRC16 Control Register (CRC_CRC16CTRL)
107
Table 7-1 CRC Register Overview
107
CRC16 Input Data Register (CRC_CRC16DAT)
108
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
108
LRC Result Register (CRC_LRC)
109
Advanced-Control Timers (TIM1)
110
TIM1 Introduction
110
Main Features of TIM1
110
TIM1 Function Description
111
Time-Base Unit
111
Figure 8-1 Block Diagram of TIM1
111
Prescaler Description
112
Counter Mode
112
Figure 8-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
112
Up-Counting Mode
112
Figure 8-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
113
Down-Counting Mode
115
Figure 8-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
115
Center-Aligned Mode
115
Figure 8-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
116
Repetition Counter
117
Figure 8-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
117
Figure 8-8 Repeat Count Sequence Diagram in Down-Counting Mode
118
Figure 8-9 Repeat Count Sequence Diagram in Up-Counting Mode
119
Figure 8-10 Repeat Count Sequence Diagram in Center-Aligned Mode
119
Clock Selection
120
Figure 8-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
120
Figure 8-12 TI2 External Clock Connection Example
121
Figure 8-13 Control Circuit in External Clock Mode 1
122
Figure 8-14 External Trigger Input Block Diagram
122
Capture/Compare Channels
123
Figure 8-15 Control Circuit in External Clock Mode 2
123
Figure 8-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
124
Figure 8-17 Capture/Compare Channel 1 Main Circuit
125
Input Capture Mode
126
Figure 8-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
126
Figure 8-19 Output Part of Channelx (X= 4)
126
PWM Input Mode
127
Forced Output Mode
128
Output Compare Mode
128
Figure 8-20 PWM Input Mode Timing
128
PWM Mode
130
PWM Center-Aligned Mode
130
Figure 8-21 Output Compare Mode, Toggle on OC1
130
Figure 8-22 Center-Aligned PWM Waveform (AR=8)
131
Figure 8-23 Edge-Aligned PWM Waveform (APR=8)
132
One-Pulse Mode
133
Figure 8-24 Example of One-Pulse Mode
133
Clearing the Ocxref Signal on an External Event
134
Complementary Outputs with Dead-Time Insertion
135
Figure 8-25 Clearing the Ocxref of Timx
135
Figure 8-26 Complementary Output with Dead-Time Insertion
136
Break Function
137
Debug Mode
138
Figure 8-27 Output Behavior in Response to a Break
138
Timx and External Trigger Synchronization
139
Slave Mode: Reset Mode
139
Figure 8-28 Control Circuit in Reset Mode
139
Slave Mode: Trigger Mode
139
Slave Mode: Gated Mode
140
Figure 8-29 Control Circuit in Trigger Mode
140
Figure 8-30 Control Circuit in Gated Mode
141
Timer Synchronization
142
6-Step PWM Generation
142
Figure 8-31 Control Circuit in Trigger Mode + External Clock Mode2
142
Timx Register Description(X=1)
143
Register Overview
143
Table 8-1 Register Overview
143
Figure 8-32 6-Step PWM Generation, COM Example (OSSR=1)
143
Control Register 1 (Timx_Ctrl1)
145
Control Register 2 (Timx_Ctrl2)
147
Slave Mode Control Register (Timx_Smctrl)
148
Interrupt Enable Registers (Timx_Dinten)
150
Table 8-2 Timx Internal Trigger Connection
150
Status Registers (Timx_Sts)
151
Event Generation Registers (Timx_Evtgen)
153
Capture/Compare Mode Register 1 (Timx_Ccmod1)
154
Capture/Compare Mode Register 2 (Timx_Ccmod2)
158
Capture/Compare Enable Registers (Timx_Ccen)
159
Table 8-3 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
161
Counters (Timx_Cnt)
162
Prescaler (Timx_Psc)
162
Auto-Reload Register (Timx_Ar)
162
Repeat Count Registers (Timx_Repcnt)
163
Capture/Compare Register 1 (Timx_Ccdat1)
163
Capture/Compare Register 2 (Timx_Ccdat2)
164
Capture/Compare Register 3 (Timx_Ccdat3)
164
Capture/Compare Register 4 (Timx_Ccdat4)
165
Break and Dead-Time Registers (Timx_Bkdt)
165
Capture/Compare Mode Registers 3(Timx_Ccmod3)
167
Capture/Compare Register 5 (Timx_Ccdat5)
168
General-Purpose Timers (TIM3)
169
General-Purpose Timers Introduction
169
Main Features of General-Purpose Timers
169
General-Purpose Timer Description
170
Time-Base Unit
170
Figure 9-1 Block Diagram of Timx(X=3
170
Counter Mode
171
Figure 9-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
171
Figure 9-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
172
Figure 8-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
173
Figure 9-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
173
Figure 9-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
174
Figure 9-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
175
Clock Selection
176
Figure 9-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
176
Figure 9-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
177
Figure 9-9 TI2 External Clock Connection Example
178
Figure 9-10 Control Circuit in External Clock Mode 1
179
Figure 9-11 External Trigger Input Block Diagram
179
Capture/Compare Channels
180
Figure 9-12 Control Circuit in External Clock Mode 2
180
Figure 9-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
181
Figure 9-14 Capture/Compare Channel 1 Main Circuit
182
Input Capture Mode
183
Figure 9-15 Output Part of Channelx (X = 1,2;Take Channel 1 as an Example
183
PWM Input Mode
184
Forced Output Mode
185
Output Compare Mode
185
Figure 9-16 PWM Input Mode Timing
185
Figure 9-17 Output Compare Mode, Toggle on OC1
186
PWM Mode
187
Figure 9-18 Center-Aligned PWM Waveform (AR=8)
188
One-Pulse Mode
189
Figure 9-19 Edge-Aligned PWM Waveform (APR=8)
189
Figure 9-20 Example of One-Pulse Mode
190
Clearing the Ocxref Signal on an External Event
191
Figure 9-21 Control Circuit in Reset Mode
191
Debug Mode
192
Timx and External Trigger Synchronization
192
Timer Synchronization
192
Figure 9-22 Block Diagram of Timer Interconnection
192
Figure 9-23 TIM3 Gated by OC1REF of TIM1
193
Figure 9-24 TIM3 Gated by Enable Signal of TIM1
194
Figure 9-25 Trigger TIM3 with an Update of TIM1
195
Timx Register Description(X=3)
196
Register Overview
196
Table 9-1 Register Overview
196
Figure 9-26 Triggers Timers 1 and 3 Using the TI1 Input of TIM1
196
Control Register 1 (Timx_Ctrl1)
197
Control Register 2 (Timx_Ctrl2)
199
Slave Mode Control Register (Timx_Smctrl)
200
Interrupt Enable Registers (Timx_Dinten)
202
Table 9-2 Timx Internal Trigger Connection
202
Status Registers (Timx_Sts)
203
Event Generation Registers (Timx_Evtgen)
204
Capture/Compare Mode Register 1 (Timx_Ccmod1)
205
Capture/Compare Enable Registers (Timx_Ccen)
208
Counters (Timx_Cnt)
209
Table 9-3 Output Control Bits of Standard Ocx Channel
209
Prescaler (Timx_Psc)
210
Auto-Reload Register (Timx_Ar)
210
Capture/Compare Register 1 (Timx_Ccdat1)
210
Capture/Compare Register 2 (Timx_Ccdat2)
211
Basic Timers (TIM6)
211
Basic Timers Introduction
211
Main Features of Basic Timers
211
Basic Timers Description
212
Time-Base Unit
212
Figure 10-1 Block Diagram of TIM6
212
Counter Mode
213
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
213
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
214
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
215
Clock Selection
216
Debug Mode
216
Timx Register(X=6)
216
Figure 10-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
216
Register Overview
217
Control Register 1 (Timx_Ctrl1)
217
Interrupt Enable Registers (Timx_Dinten)
218
Status Registers (Timx_Sts)
219
Event Generation Registers (Timx_Evtgen)
219
Counters (Timx_Cnt)
219
Prescaler (Timx_Psc)
220
Automatic Reload Register (Timx_Ar)
220
Independent Watchdog (IWDG)
221
IWDG Introduction
221
IWDG Main Features
221
IWDG Function Description
222
Register Access Protection
222
Figure 11-1 Functional Block Diagram of the Independent Watchdog Module
222
Debug Mode
223
Low Power Consumption
223
User Interface
223
Operate Flow
223
IWDG Configuration Flow
224
IWDG Registers
224
IWDG Register Map
224
Table 11-1 IWDG Overtime Time at 32Khz
224
Table 11-2 IWDG Register Map and Reset Values
224
IWDG Key Register (IWDG_KEY)
225
IWDG Pre-Scaler Register (IWDG_PREDIV)
225
IWDG Reload Register (IWDG_RELV)
226
IWDG Status Register (IWDG_STS)
226
IWDG Freeze Register (IWDG_FREEZE)
227
Analog to Digital Conversion (ADC)
228
ADC Introduction
228
Main Features
228
ADC Function Description
228
Table 12-1 ADC Pins
229
Figure 12-1 Block Diagram of ADC
229
ADC Clock
230
ADC Switch Control
230
Channel Selection
230
Internal Channel
230
Single Conversion Mode
231
Continuous Conversion Mode
231
Timing Diagram
231
Analog Watchdog
232
Scan Mode
232
Table 12-2 Analog Watchdog Channel Selection
232
Figure 12-2 Timing Diagram
232
Data Aligned
233
Programmable Channel Sampling Time
233
Externally Triggered Conversion
233
Table 12-3 Right-Align Data
233
Table 12-4 Left-Align Data
233
Table 12-5 ADC Is Used for External Triggering of Regular Channels
233
ADC Interrupt
234
ADC Registers
234
Table 10-1 Register Overview
234
Table 12-6 ADC Interrupt
234
Table 12-7 Register Overview
234
ADC Status Register (ADC_STS)
235
ADC Control Register 1 (ADC_CTRL1)
236
ADC Control Register 2 (ADC_CTRL2)
237
ADC Control Register 3 (ADC_CTRL3)
238
ADC Sampling Time Register (ADC_ SAMPT)
239
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
240
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
240
ADC Regular Data Register X (Adc_Datx) (X= 0
241
Comparator (COMP)
242
COMP System Connection Block Diagram
242
COMP Features
242
Figure 13-1 Comparator System Connection Diagram
242
COMP Configuration Process
243
COMP Working Mode
243
Independent Comparator
243
Comparator Interconnection
243
Interrupt
244
COMP Registers
244
Table 13-1 Register Overview
244
COMP Interrupt Enable Register (COMP_INTEN)
245
COMP Interrupt Status Register (COMP_INTSTS)
245
COMP Lock Register (COMP_LOCK)
246
COMP Control Register (COMP_CTRL)
246
COMP Filter Control Register (COMP_FILC)
247
COMP Filter Clock Register (COMP_FILP)
248
Inter-Integrated Circuit Bus(I 2 C)
249
Introduction
249
Main Features
249
Function Description
249
SDA and SCL Line Control
249
Software Communication Process
250
Figure 14-1 I2C Functional Block Diagram
251
Start and Stop Conditions
251
Figure 14-2 I2C Bus Protocol
251
Clock Synchronization and Arbitration
251
Clock Synchronization
252
Figure 14-3 Slave Transmitter Transfer Sequence Diagram
254
Figure 14-4 Slave Receiver Transfer Sequence Diagram
255
Figure 14-5 Master Transmitter Transfer Sequence Diagram
257
Figure 14-6 Master Receiver Transfer Sequence Diagram
259
Error Conditions Description
260
Packet Error Check
261
Noise Filter
261
Interrupt Request
261
Table 14-1 I 2 C Interrupt Request
261
I2C Registers
262
I2C Register Overview
262
Table 14-2 I2C Register Overview
262
I2C Control Register 1 (I2C_CTRL1)
263
I2C Control Register 2 (I2C_CTRL2)
265
I2C Own Address Register 1 (I2C_OADDR1)
266
I2C Own Address Register 2 (I2C_OADDR2)
266
I2C Data Register (I2C_DAT)
267
I2C Status Register 1 (I2C_STS1)
267
I2C Status Register 2 (I2C_STS2)
270
I2C Clock Control Register (I2C_CLKCTRL)
271
I2C Rise Time Register (I2C_TMRISE)
272
I2C Filter Control Register (I2C_GFLTRCTRL)
272
I2C Master Receive Byte Register (I2C_BYTENUM)
273
Universal Asynchronous Receiver Transmitter (UART)
274
Introduction
274
Main Features
274
Functional Block Diagram
275
Function Description
275
Figure 15-1 UART Block Diagram
275
UART Frame Format
276
Figure 15-2 Word Length = 8 Setting
276
Figure 15-3 Word Length = 9 Setting
276
Transmitter
277
Table 15-1 Stop Bit Configuration
277
Figure 15-4 Stop Bit Configuration
277
Single Byte Communication
278
Receiver
279
Start Bit Detection
279
Figure 15-5 TXC/TXDE Changes During Transmission
279
Figure 15-6 Start Bit Detection
280
Table 15-2 Data Sampling for Noise Detection
281
Generation of Fractional Baud Rate
282
Table 15-3 Error Calculation When Setting Baud Rate
282
Even Parity
283
Receiver's Tolerance Clock Deviation
283
Parity Control
283
Table 15-4 When Div_Decimal = 0. Tolerance of UART Receiver
283
Table 15-5 When Div_Decimal != 0. Tolerance of UART Receiver
283
Table 15-6 Frame Format
283
Multiprocessor Communication
284
Idle Line Detection
284
Figure 15-7 Mute Mode Using Idle Line Detection
285
Single-Line Half-Duplex Communication
286
Interrupt Request
286
UART Mode Configuration
286
Table 15-7 UART Interrupt Request
286
Table 15-8 UART Mode Setting
286
Figure 15-8 Mute Mode Detected Using Address Mark
286
UART Registers
287
UART Register Map
287
UART Status Register (UART_STS)
287
Table 15-9 UART Register Map and Reset Values
287
UART Data Register (UART_DAT)
289
UART Baud Rate Configuration Register (UART_BRCF)
290
UART Control Register 1(UART_CTRL1)
290
UART Control Register 2(UART_CTRL2)
292
UART Control Register 3(UART_CTRL3)
292
Serial Peripheral Interface (SPI)
294
SPI Introduction
294
SPI Main Features
294
SPI Function Description
295
General Description
295
Figure 16-1 SPI Block Diagram
295
Figure 16-2 Slave Selects Management of Hardware/Software
296
Figure 16-3 Master and Slave Applications
297
SPI Work Mode
298
Figure 16-4 Data Clock Timing Diagram
298
Figure 16-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full Duplex Mode
299
Figure 16-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode
300
Figure 16-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode
301
Figure 16-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in Full Duplex Mode
302
Figure 16-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional
302
Status Flag
305
Figure 16-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted
305
Turn off the SPI
306
Error Flag
306
SPI Interrupt
307
SPI Register
307
SPI Register Overview
307
SPI Control Register 1 (SPI_CTRL1)
307
Table 16-1 SPI Interrupt Request
307
Table 16-2 SPI Register Overview
307
SPI Control Register 2 (SPI_CTRL2)
309
SPI Status Register (SPI_STS)
310
SPI Data Register (SPI_DAT)
311
Beeper
312
Introduction
312
Function Description
312
Beeper Registers
312
Beeper Register Overview
312
Beeper Control Register (BEEPER_CTRL)
312
Table 17-1 Beeper Register Overview
312
Debug Support (DBG)
314
Overview
314
Figure 18-1 N32G003 Level and Cortex®-M0 Level Debugging Block Diagram
314
SWD Function
315
Pin Assignment
315
Unique Device Serial Number (UID)
316
Introduction
316
UID Register
316
UCID Register
316
DBGMCU_ID Register
316
Table 19-1 DBGMCU_ID Bit Description
316
Version History
318
Notice
319
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