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RTD2136N-CG
5
Power
D03
D03
3.3VS
3.3VS
2A
VL1
0_06
VL3
.
0_06
AVCC33
.
DVCC33
DVCC33
D03
VC17
VC19
6-19-31001-245
VC16
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
0.1u_10V_X7R_04
D03
D03
Note:
VR23
0_04
HPD
1. Entire trace of Panel VCC should be wider than 80-mil
5,13
EDP_HPD
LVDS
VC8
0.1u_10V_X7R_04
DAUXn
5
EDP_AUXN
VC9
0.1u_10V_X7R_04
DAUXp
5
EDP_AUXP
eDP
ER12
0_04
DP_AUX#
13
ER11
0_04
DP_AUX
13
ER9
0_04
DP_TXN0
13
ER10
0_04
DP_TXP0
13
LVDS
VC10
0.1u_10V_X7R_04
DRX0p
5
EDP_TXP_0
VC11
0.1u_10V_X7R_04
DRX0n
5
EDP_TXN_0
VC12
0.1u_10V_X7R_04
DRX1p
5
EDP_TXP_1
VC13
0.1u_10V_X7R_04
DRX1n
5
EDP_TXN_1
eDP
ER8
0_04
DP_TXP1
13
ER7
0_04
DP_TXN1
13
eDP
,BRIGHTNESS
EDP CONNECTOR
eDP
ER3
0_04
PANEL_PW M
LVDS
BRIGHTNESS_EC_PS
VR27
0_04
35
EDP_BRIGHTNESS
VR28
*0_04
48
BRIGHTNESS
From EC
,
VR26
*100K_04
Mode Configure Table(Power On Latch)
MODE_CFG0(PIN47)
0
1
0
X
EP MODE
MODE_CFG1(PIN48)
1
ROM ONLY MODE
EEPROM MODE
3.3VS
3.3VS
VR18
VR21
*4.7K_04
4.7K_04
RTD2136 Supports three operation mode for system design.
Reserved 4.7K resistor pull up/low for mode selection
VR19
VR22
ROM ONLY Mode
: PIN47 4.7K pull low, PIN48 4.7K pull high
4.7K_04
*4.7K_04
EP Mode
: PIN47 4.7K pull high, PIN48 4.7K pull low
EEPROM Mode
: PIN47 4.7K pull high, PIN48 4.7K pull high
PIN47
PIN48
5
4
3
2A
VC4
Cap
0.1u_10V_X7R_04
VU1
HPD
1
DP_HPD
TEST_MODE
2
TEST_MODE
3
DAUXn
AUX_CH_N
VR24
DAUXp
4
100K_04
AUX_CH_P
AVCC33
5
DP_V33
RTD2136N-CG
6
DP_GND
DRX0p
7
LANE0_P
DRX0n
8
LANE0_N
Cap
DRX1p
9
LANE1_P
10
DRX1n
LANE1_N
VCCK_V12
11
DP_V12
DP_REXT
12
DP_REXT
VC6
0.1u_10V_X7R_04
VR25
Cap
12K_1%_04
Note:
1. Cap should be closed to chip
PANEL_PW M
13
VR14
10K_04
DVCC33
D03
Cap
Cap
Cap
Note:
Entire trace of Panel VCC should be wider than 80-mil
EEPROM Mode
I2C address=0xA8
In EEPROM mode, an additional EEPROM is needed.
EEPROM should configure with following condition.
1- EEPROM with a size 8K-Byte
2- EEPROM device should be 2-byte addressing device
3- Slave address should configure as 0xA8
4
3
2
ENBLT
ENBLT
VR15
10K_04
D03
LVDS-L0N
LVDS-L0N
LVDS-L0P
LVDS-L0P
LVDS-L1N
LVDS-L1N
Single link
LVDS-L1P
LVDS-L1P
LVDS
LVDS-L2N
LVDS-L2N
36
LVDS-LCLKN
LVDS-L2P
TXOC-
LVDS-L2P
35
LVDS-LCLKP
LVDS-LCLKN
LVDS-LCLKN
TXOC+
LVDS-LCLKP
LVDS-LCLKP
34
TXO3-
33
LVDS-U0N
LVDS-U0N
TXO3+
LVDS-U0P
LVDS-U0P
32
LVDS-U0N
TXE0-
LVDS-U1N
LVDS-U1N
31
LVDS-U0P
LVDS-U1P
LVDS-U1P
TXE0+
30
LVDS-U1N
LVDS-U2N
LVDS-U2N
TXE1-
LVDS-U2P
LVDS-U2P
29
LVDS-U1P
TXE1+
LVDS-UCLKN
LVDS-UCLKN
28
LVDS-U2N
LVDS-UCLKP
LVDS-UCLKP
TXE2-
27
LVDS-U2P
TXE2+
26
LVDS-UCLKN
TXEC-
P_DDC_CLK
P_DDC_CLK
25
LVDS-UCLKP
P_DDC_DATA
TXEC+
P_DDC_DATA
2A
LVDS_PLVDD_EN
VC1
*4.7u_6.3V_X5R_06
RTD2136N-CG
To LVDS Connector
Dual Mode Regulator Configuration
2.2-uH(L)
0 Olm(R)
SWR
Connect
NC
LDO
NC
Connect
SWR MODE
LVDS_PLVDD_EN
13
VL2
*BCNR3010C-2R2M
1A
1
2
PIN17
6-19-41001-019
VCCK_V12
LDO MODE
1A
D03
PIN17
VR20
0_06
1.C516, C511 Capacitors should be closed to PIN17
3.3VS
3,9,10,11,12,13,15,16,17,32,33,34,35,37,38,39,40,41,43,44,45,46,48,49,50,51,54,57
PLVDD
13
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[14] RTD2136N-CG
[14] RTD2136N-CG
[14] RTD2136N-CG
Size
Size
Size
Document Number
Document Number
Document Number
6-71-P6500-D03
6-71-P6500-D03
6-71-P6500-D03
A3
A3
A3
P650SE
P650SE
P650SE
Date:
Date:
Date:
W ednesday, August 20, 2014
W ednesday, August 20, 2014
W ednesday, August 20, 2014
2
Schematic Diagrams
1
13
D
13
13
13
13
13
13
13
13
13
13
13
13
Sheet 14 of 72
13
13
RTD2136N-CG
13
13
C
13
13
PLVDD
2A
VR1
*0_06
VR3
*1K_04
B
A
Rev
Rev
Rev
D03
D03
D03
Sheet
Sheet
Sheet
14
14
14
of
of
of
77
77
77
1
RTD2136N-CG B - 15
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