Processor 7/7- Rsvd - Clevo P650SE Service Manual

Processor 7/7- RSVD

5
CFG STRAPS FOR PROCESSOR
D
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
CFG2 R335 *1K_04
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
C
CFG4 AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
CFG4 R333 1K_04
PCIE PORT BIFURCATION STRAPS
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B
CFG5 R334 *1K_04
CFG6 R331 *1K_04
DEFENSIVE PULL DOWN SITE
CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG7 R332 *1K_04
A
5
4 3
Haswell Processor 7/7 ( RESERVED )
HASWELL_BGA_E
U104K
F1
RSVD_TP
E1
RSVD_TP
BE4 A5
RSVD_TP RSVD_TP
BD3 A6
RSVD_TP RSVD_TP
F6 R54
RSVD_TP CFG_RCOMP
G6 Y52
RSVD_TP CFG16
V53
CFG18
G21 Y51
RSVD_TP CFG17
G24 V52
RSVD_TP CFG19
TESTLO_F21 F21
TESTLO_F21
G19 B50
VSS RSVD
F51 AH49
VSS RSVD
F52 AM48
VSS RSVD
F22 AU27
VCORE VCC RSVD
AU26
RSVD
L52 BD4
RSVD_TP RSVD
L53 BC4
RSVD_TP RSVD
AL6
RSVD
L51 F8
RSVD_TP RSVD
F24
RSVD_TP
F25
RSVD_TP
TESTLO_F20 F20
TESTLO_F20
AG49 F16
CFG0 RSVD
AD49
CFG1
CFG2 AC49
CFG2
CFG3 AE49
CFG3
Y50
CFG4
CFG4
CFG5 AB49
CFG5
R336 CFG6 V51 G12
CFG6 RSVD_TP
*1K_04 CFG7 W51 G10
CFG7 RSVD_TP
Y49
CFG8
Y54 H54
CFG9 VSS
Y53 H53
CFG10 VSS
W53
CFG11
U53 H51
CFG12 VSS
V54 H52
CFG13 VSS
R53
CFG14
R52 N51
CFG15 RSVD
G53
RSVD
L50 H50
RSVD RSVD
L49
RSVD
E5
RSVD
11 OF 12
TESTLO_F20
R241
TESTLO_F21 R244
CFG_RCOMP
R743
4 3
2 1
HASWELL_BGA_E
U104L
A3
DAISY_CHAIN_NCTF_A3
A4
DAISY_CHAIN_NCTF_A4
CFG_RCOMP
DAISY_CHAIN_NCTF_BF51
DAISY_CHAIN_NCTF_BF52
A51
DAISY_CHAIN_NCTF_A51 DAISY_CHAIN_NCTF_BF53
A52
DAISY_CHAIN_NCTF_A52
A53
DAISY_CHAIN_NCTF_A53 DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_C3
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_C54
DAISY_CHAIN_NCTF_D1
B52
DAISY_CHAIN_NCTF_B52
B53
DAISY_CHAIN_NCTF_B53 DAISY_CHAIN_NCTF_D54
B54
DAISY_CHAIN_NCTF_B54
BC1
DAISY_CHAIN_NCTF_BC1
BC54
DAISY_CHAIN_NCTF_BC54
BD1
DAISY_CHAIN_NCTF_BD1
BD54
DAISY_CHAIN_NCTF_BD54
BE1
DAISY_CHAIN_NCTF_BE1 RSVD
BE2
DAISY_CHAIN_NCTF_BE2 RSVD
BE3
DAISY_CHAIN_NCTF_BE3 RSVD
BE52
DAISY_CHAIN_NCTF_BE52 RSVD
BE53
DAISY_CHAIN_NCTF_BE53 RSVD
BE54
DAISY_CHAIN_NCTF_BE54 RSVD
BF2
DAISY_CHAIN_NCTF_BF2 RSVD
BF3
DAISY_CHAIN_NCTF_BF3 RSVD
BF4
DAISY_CHAIN_NCTF_BF4
12 OF 12
49.9_1%_04
49.9_1%_04
49.9_1%_04
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[08] Processor 7/7-RSVD [08] Processor 7/7-RSVD [08] Processor 7/7-RSVD
Size Size Size Document Number Document Number Document Number
6-71-P6500-D03 6-71-P6500-D03 6-71-P6500-D03
6,7,57 VCORE
A3 A3 A3 P650SE P650SE P650SE
Date: Date: Date: Monday, August 18, 2014 Monday, August 18, 2014 Monday, August 18, 2014
2 1
Schematic Diagrams
D
BF51
BF52
BF53
C1
C2
C3
C54
D1
D54
Sheet 8 of 72
Processor 7/7-
AN35
AN37
AF9 C
RSVD
AE9
G14
G17
AD45
AG45
B
A
Rev Rev Rev
D03 D03 D03
Sheet Sheet Sheet 8 8 8 of of of 77 77 77
Processor 7/7- RSVD B - 9