Clevo P650SE Service Manual page 54

Schematic Diagrams
Processor 2/7- CLK, MISC
D
Sheet 3 of 72
Processor 2/7-CLK,
C
S3 circuit:- DRAM_RST# to memory
should be high during S3
MISC
B
Buffered reset to CPU
A
B - 4 Processor 2/7- CLK, MISC
5 4
Haswell Processor 2/7 ( MISC,JTAG,CLK )
37,48 H_PECI
H_PROCHOT#
57 H_PROCHOT#
37 H_THRMTRIP#
34 H_PM_SYNC
37 H_CPUPW RGD
PMSYS_PW RGD_BUF
PCH_PLTRST_CPU
37 PCH_PLTRST_CPU
BUF_CPU_RST#
40
40
40
40
VDDQ
R360 *0_04 R365
1K_04
BSS138 ( VGS 1.5V )
Q21
2SK3018S3
CPUDRAMRST# S D
R364 1K_04
R359
DDR3_DRAMRST# 9,10,11,12
4.99K_1%_04
DRAMRST_CNTRL 33
C494
0.047u_10V_X7R_04
R757 *2K_1%_04 BUF_CPU_RST#
35 PLT_RST#
R754
*1K_1%_04
5 4
3
U104B HASWELL_BGA_E
MISC
PROC_DETECT# C51
PROC_DETECT
H_CATERR#
G50
CATERR
G51
R351 *10mil_short
PECI
R349 56_1%_04 E50
PROCHOT
R741 *10mil_short D53
THERMTRIP
R742 *100_1%_04
1.05VS
R752 *10mil_short D52
PM_SYNC
H_CPUPW RGD_R
R352 *10mil_short F50
PWRGOOD
AP48
R355 0_04
SM_DRAMPWROK
R746 0_04 CPU_RST# L54
PLTRSTIN
R747 *0_04
DPLL_REF_CLKN
R194 0_04 AC6
CLK_DPNS_N
DPLL_REF_CLKN
R195 0_04 DPLL_REF_CLKP AE6
CLK_DPNS_P
DPLL_REF_CLKP
R200 0_04 SSC_DPLL_REF_CLKN V6
CLK_DP_N SSC_DPLL_REF_CLKN
R201 0_04 SSC_DPLL_REF_CLKP Y6
CLK_DP_P SSC_DPLL_REF_CLKP
AB6
40 CLK_EXP_N
BCLKN
AA6
40 CLK_EXP_P
BCLKP
2 OF 12
S3 circuit:- DRAM PWR GOOD logic
3.3V 3.3V
C500
VDDQ
R366 R354
R372
1.82K_1%_04
1
34 PM_DRAM_PW RGD
4 PMSYS_PW RGD_BUF
2
R370
U16
*MC74VHC1G08DFT1G R369
*39_04
R368 0_04
Q25
G
15,17,52,54,55 SUSB
*2SK3018S3
H_PROCHOT#
Q20
G C502
48 H_PROCHOT_EC
2SK3018S3
47P_50V_NPO_04
R348
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
3.3VS 9,10,11,12,13,14,15,16,17,32,33,34,35,37,38,39,40,41,43,44,45,46,48,49,50,51,54,57
3.3V 2,13,30,32,41,42,43,44,45,49,50,51,52,54,55,58,59,60
VDDQ 6,9,10,11,12,52
1.05VS 6,38,39,55,57
VCCIO_OUT 6,57
3
2 1
PU/PD for JTAG signals
XDP_TMS
R328 51_04
XDP_TDI_R R329 51_04
XDP_PREQ# R330 *51_04
XDP_TDO_R
R327 51_04
XDP_TCLK
R744 51_04
XDP_TRST# R745 51_04
BB51 SM_RCOMP_0 XDP_TDO_R R326 *100_04
SM_RCOMP0
BB53 SM_RCOMP_1
SM_RCOMP1
SM_RCOMP_2
BB52
SM_RCOMP2
BE51
CPUDRAMRST#
SM_DRAMRST
N53 XDP_PRDY#
PRDY
XDP_PREQ# XDP_DBR_R
N52 1K_04 R751
PREQ
XDP_TCLK
N54
TCK
M51 XDP_TMS
TMS
M53 XDP_TRST#
TRST
N49 XDP_TDI_R
DDR3 Compensation Signals
TDI
XDP_TDO_R
M49
TDO
F53 XDP_DBR_R
DBR
R51 XDP_BPM0 SM_RCOMP_0 R358 100_1%_04
BPM#0
XDP_BPM1
R50
BPM#1
XDP_BPM2 SM_RCOMP_1
P49 R356 75_1%_04
BPM#2
N50 XDP_BPM3
BPM#3
R49 XDP_BPM4 SM_RCOMP_2 R357 100_1%_04
BPM#4
P53 XDP_BPM5
BPM#5
XDP_BPM6
U51
BPM#6
P51 XDP_BPM7
BPM#7
Processor Pullups/Pull downs
H_PROCHOT# R350 62_04
H_CPUPW RGD_R
R373 10K_04
C503 *0.1u_16V_Y5V_04
TRACE WIDTH 10MIL, LENGTH <500MILS
Supports external Graphics
No integrated graphic and eDP
1.05VS
R371
DPLL_REF_CLKN
R203 *1K_04
*100K_04
R211 *1K_04 DPLL_REF_CLKP
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
VCCIO_OUT
SSC_DPLL_REF_CLKP
R202 *10K_04
R199 *10K_04 SSC_DPLL_REF_CLKN
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[03] Processor 2/7-CLK,MISC [03] Processor 2/7-CLK,MISC [03] Processor 2/7-CLK,MISC
Size Size Size Document Number Document Number Document Number
6-71-P6500-D03 6-71-P6500-D03 6-71-P6500-D03
A3 A3 A3 P650SE P650SE P650SE
Date: Date: Date: Monday, August 18, 2014 Monday, August 18, 2014 Monday, August 18, 2014 Sheet Sheet Sheet 3 3 3
2 1
1.05VS
D
3.3VS
VCCIO_OUT
C
B
A
Rev Rev Rev
D03 D03 D03
of of of 77 77 77