FabiaTech FX5653 User Manual page 81

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Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)
Divisor Latch (LS, MS)
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
Desired Baud
Rate
300
600
1200
1800
2400
3600
4800
9600
14400
19200
28800
38400
57600
115200
LS MS
Bit 0 Bit 8
Bit 1 Bit 9
Bit 2 Bit 10
Bit 3 Bit 11
Bit 4 Bit 12
Bit 5 Bit 13
Bit 6 Bit 14
Bit 7 Bit 15
Divisor Used to Generate 16x
Clock
384
192
96
64
48
32
24
12
8
6
4
3
2
1
77