Lightware DA2DVI-Pro User Manual page 25

Serial Parameters
PLL Bandwidth
Output strength
Polarity
Parallel Parameters
De-skewing
PLL Filter
Sync
Output Signal
Adjusts the TMDS PLL filter bandwith. SW 2 and 3 of the
DIP switch also adjust this value on the rear panel of the
DA2DVI-Pro. If the incoming signal has too much jitter
resulting from a low quality source, then a higher PLL
fileter bandwidth may be necessary. The default value of
4 MHz should provide the best results in most cases.
CAUTION! Setting a higher frequency slightly decreases
the quality of the output signal
Adjusts the internal clock or data drive strength. The
default setting of High should always be applied.
SW 8 of the DIP switch adjusts this setting on the rear
panel of the DA2DVI-Pro. This is a coarse adjustment of
the deskew value. This setting shifts the phase of the
internal clock signal by 180 degrees.
SW 4, 5 and 6 of the DIP switch adjust this value on the
rear panel of the DA2DVI-Pro. If the clock and pixel data
are not perfectly aligned in the internal parallel signal,
then there's a possibility to add some skew between
them in both directions. There right value may depend on
the resolution and pixel clock. A default setting of -2
should provide the best result in most cases.
SW 7 of the DIP switch enables this setting on the rear
panel of the DA2DVI-Pro. It is recommended to turn on
the Pixel PLL at all times. If the quality of the incoming
signal is too low and the other settings could not improve
the quality, then disabling the Pixel PLL may be
necessary. Different values adjust the pixel PLL filter
frequency. Using value 4 is strongly recommended.
Always use the ON setting.
This setting is used to mute the output signal.
DA2DVI-Pro
User's Manual Rev. 1.3
Page 25 / 43