Main Board Theory - Lexicon RV-8 Service Manual

Lexicon
RV-8 MAIN BOARD THEORY
This section provides a detailed description of the design theory embodied in the RV-8 Main Board. Each
section of this document will discuss the theory of each functional subset of this board and will reference
a schematic sheet for each block. The schematic set being referenced is at a minimum revision level of 6.
The RV-8 Main Board incorporates the following features:
•
Command and control of the entire RV-8 system
•
Digital audio inter-system routing via FPGA
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Front Panel display control, button monitoring, and LED display control
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Two expansion ports
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Amplifier environmental and power monitoring and control
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User and debug access via two RS-232 serial ports
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Four coaxial and four optical S/PDIF input ports
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One coaxial and one optical S/PDIF Record Zone output
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One Composite Video Zone 3 output
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Two remote power outputs
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Two Phase Locked Voltage Controlled Oscillators for master audio clock generation
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IR remote control sensing and discrimination from the front panel and Zone Two
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"Canned" Algorithm Surround Processing via a single Crystal Semiconductors DSP engine
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Lexicon specific supplemental DSP via two Analog Devices SHARC DSP engines.
START-UP CONDITIONS
Power On and Boot Procedure
Once the unit is powered up, the reset generator U31 provides both active low and active high reset
signals of approximately 3ms duration. During this interval, the CPU processor (U33) is held in an inactive
state as well as the three DSP engines, and the FPGA. This reset is also passed along to all of the
remaining boards in the system. Once this reset interval has passed, the processor and FPGA are ready
for further instruction. The DSP engines remain in reset, however, and are not released from this state
until commanded by the system software. The CPU then begins booting from the on-board 1Mx16 Flash,
U26. Diagnostic testing is run on the on-board DRAM (U42). If the test passes, test LED D10 will light; it
will flash if the test fails. The bulk of the boot and application software is then loaded from the Flash into
this DRAM and a checksum test is performed. If this test passes, test LED D11 will light, flash if the test
fails. Internal registers of the processor device are then configured. These include the following:
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Bus State Controller
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Wait State Controller
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DRAM Configuration (the default conditions are now replaced with optimized settings)
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Serial Communication Ports 1 and 2
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Pin Function Control
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General Purpose I/O.
The processor then checks the status of PE[3:1] (88:86) to determine which start-up configuration has
been chosen by the user. If these port pins read as all low, then the processor continues with the normal
boot procedure.
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