Lexicon RV-8 Service Manual page 90

implemented in W3, W4, and W5. The following table illustrates the various modes available to the
developer.
W3 W4
Uninstalled 1-2
Open 2 - 3
Open Open
Open 2 - 3
1 - 2 1 - 2
FLASH (U26)
The FLASH RAM used in this product is a 1Mx16 120nS device. There is a sector of memory of
16Kwords available at the bottom of the memory array. This is intended for use as a boot sector, and can
be write protected to prevent erasure when updates to the system or algorithm software are being
programmed. This write protect is enforced or disabled by the state of the WP/ pin (14). This pin is under
software control by the CPU. When this pin is low, protection is enforced. When high, the boot sector may
be erased and re-programmed.
The RYBY/ pin (15) is an output flag of the internal status of the device. When this pin is low, it indicates
that the Flash is in the middle of an erase or programming cycle (busy). When this pin returns to a high
state, it indicates that the operation at hand has been completed and the device contents may be read in
the same manner as an EEPROM. The WE/ (11), CE/ (26), and OE/ (28) have the same function as
those on an EEPROM.
Erasure or in-circuit programming is accomplished by executing the erase or program command
sequence. These sequences initiate the proper embedded algorithm that ensures proper execution of the
desired command.
The RESET/ pin (12) is tied to the system level power-on reset. When this pin is low, it suspends any
operation that is in progress, and resets the internal state machines to reading array data. During power-
up, the internal state machines are set up in this manner.
The BYTE/ pin (47) is pulled high to configure the Flash as a word mode device.
The CPU fetches its start-up instructions from the boot sector of this device. Once boot-up is complete, all
system control and DSP algorithm code is accessed from here as well. Under normal operating
circumstances, CS0/ from the CPU controls the CE/ pin of this device. This signal is labeled BOOTCS/,
and it is routed to the FLASH device by jumpering pins 1 and 2 on W4. During code development cycles,
CS1/ from the CPU is routed to the CE/ pin by jumpering pins 2 and 3 on W4. In this case, the chip select
signal is labeled PROGCS/. All code outside of low level booting may be executed from the memory
space occupied by CS1/. R88 acts as a pull-up for the FLASH CE/ pin.
EEPROM (U32)
The EEPROM is a 64Kx16 1Mbit device that serves as the primary boot code source during software
development. The WE/ pin (43) is pulled high by R160 to prevent inadvertent write cycles to the device
that would corrupt the resident code. The BOOTCS/ signal is routed to the CE/ pin (3) by placing a
jumper plug between pins 1 and 2 on W5. R187 serves as a default pull-up resistor. This device is not
6-14
Boot Mode Jumper Configuration
W5
Uninstalled Default; Boot and Program Run from FLASH
1 - 2 Boot from EEPROM, FLASH Program Run
2 - 3 Boot and Program Run from ROMulator
2 - 3 Boot from ROMulator, Program Run from FLASH
Open EEPROM Boot, Program Run from ROMulator
RV-8 Service Manual
Usage