Memory; Introduction; Ram Architecture - HP 340 Series Service Manual

Memory
Introduction
Parity-checking RAM is used in the Model 340 Workstation's SPU. Either one, two, or four
HP 98268A RAM boards may be installed in the four RAM board connectors on the processor
board. The RAM boards are arrays of 4Mbytes each.
A RAM controller is located on the processor board. All RAM is auto-configuring; there are no
configuration switches to set.
Note that other Series 300 conlputer RAM boards are not supported in Model 340 Workstation
SPUs.
A picture of a RAM board is shown in Figure 3-10.
Figure 3-10. HP 98268A RAM Board
RAM Architecture
RAM consists of two logical units-one which stores the data in a RAM array and one which
controls accesses to the RAM array and interfaces it to the SPU. Physically, the RAM array
circuitry is located on a printed circuit board, called the RAM Array board, and the control
and interface circuitry is located on the processor board.
The feature of these RAM boards which distinguishes them from ordinary RAM boards is the
ability to detect and correct or report errors. This function is accornplished by the Check Bit
Generator / Checker.
The RAM boards store data as a 32-bit word with an additional four bits to store parity
information. Each byte has its own parity bit.
The Generator section of the Check Bit Generator/Checker produces the appropriate four bits
for each 32-bit data word. These bits are stored in the RAM array with the data word. When
the data word is read, the Generator/Checker reproduces the check bits and compares them
to the check bits read from the storage location. If they differ, the Generator/Checker asserts
interrupt level 7 if any error occurs.
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Functional Description