Frame Buffering And Latency - Eaton Power Xpert PXES4P Series Installation And User Manual

PXES4P Switches
ports of the PXES4P Series convenient switch support auto-cross (MDIX), and perform the
auto-cross in the auto-negotiation mode only.
Dual LEDs indicating the operating status of ports are mounted on the top as well
as end for convenience and may be viewed from any direction. There are power (PWR)
indicators for the unit to validate that the unit is turned ON. For each port, there are Link
and Activity (LK/ACT) LEDs indicating traffic that are mounted on the top of the unit as
well as the end. LEDs mounted next to each port indicate (LK/ACT as LA1, LA2, LA3,
LA4), 10/100 (ON for 100Mbps), and full/half duplex (F/H is ON for full duplex).
The DC power plug connector or "jack" is in the right rear of the chassis. The
internal DC input terminal block is also provided on the rear side of the unit.
PXES4P Switches

2.4 Frame Buffering and Latency

The PXES4P Series Switches are store-and-forward switches. Each frame (or
packet) is loaded into the Switch's memory and inspected before forwarding can occur.
This technique ensures that all forwarded frames are of a valid length and have the correct
CRC, i.e., are good packets. This eliminates the propagation of bad packets, enabling all of
the available bandwidth to be used for valid information.
While other switching technologies such as "cut-through" or "express" impose
minimal frame latency, they will also permit bad frames to propagate out to the Ethernet
segments connected. This "cut-through" technique permits collision fragment frames,
which are a result of late collisions, to be forwarded which add to the network traffic.
Since there is no way to filter frames with a bad CRC (the frame must be present in order
for CRC to be calculated), the result of indiscriminate cut-through forwarding is greater
traffic congestion, especially at peak activity. Since collisions and bad packets are more
PXES4P Switches
likely when traffic is heavy, the result of store-and-forward operation is that more
bandwidth is available for good packets when the traffic load is greatest.
When the Switch detects that its free buffer queue space is low, the Switch sends
industry standard (full-duplex only) PAUSE packets out to the devices sending packets to
cause "flow control". This tells the sending devices to temporarily stop sending traffic,
which allows a traffic catch-up to occur without dropping packets. Then, normal packet
buffering and processing resumes. This flow-control sequence occurs in a small fraction of
a second and is transparent to an observer. See Section 4.6 for additional details.
Another feature implemented in PXES4P Series Switches is a collision-based
flow-control mechanism (when operating at half-duplex only). When the Switch detects
that its free buffer queue space is low, the Switch prevents more frames from entering by
forcing a collision signal on all receiving half-duplex ports in order to stop incoming traffic.
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