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CS5960AT-X (IC571) : MPEG/Audio clock generator with VCXO
1.Pin layout
1 XIN
2 VDD
3 VCXO
4 VSS
2.Block diagram
27 XIN
OSC
XOUT
ADC
VCXO
8 bit
3.Pin function
No.
1
XIN
2
VDD
3
VCXO
4
VSS
5
16.93421053 MHz
6
13.5 MHz
7
27 MHz
8
XOUT
GM71VS17400CLT5 (IC390) : DRAM
1.Pin layout
Vcc 1
I/O1 2
I/O2 3
WE 4
RAS 5
A11 6
A10 8
A0 9
A1 10
A2 11
A3 12
Vcc 13
8 XOUT
7 27 MHz
6 13.5 MHz
5 16.93421053 MHz
/Q
7 bit
VCO
/P
11bit
PLL
/2
VDD
Symbol
Reference Crystal Input
Voltage Supply
Input Analog Control for VCXO
Ground
16.93421053-MHz clock output
13.5-MHz clock output
27-MHz clock output
Reference Crystal output
3.Pin function
Pin No.
26 Vss
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
9 12
18 A7
17 A6
16 A5
15 19
15 A4
14 Vss
OUTPUT
DIVIDERS
7 bit
VSS
Function
Function
Symbol
1
Vcc
Power(+3.3V)
2
I/O1
Data-Input/Output
3
I/O2
Data-Input/Output
4
WE
Read/Write Enable
5
RAS
Row Address Strobe
6
A11
Address Input
7
-
No Connection
Address Input
8
A10
A0 A3
Address Input
13
Vcc
Power(+3.3V)
14
Vss
Ground
A4 A8
Address Input
20
-
No Connection
21
A9
Address Input
22
OE
Output Enable
Column Address Strobe
23
CAS
24
I/O3
Data-Input/Output
25
I/O4
Data-Input/Output
26
Vss
Ground
UX-A10DVD
27 MHz
16.93421053 MHz (-3)
13.5 MHz
1-57
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