External Input Or Output Timing (No Extra Wait Sta Tes); External Input Or Output Timing - Control Data Corporation INFORMATION SYSTEMS TERMINAL II Hardware Maintenance Manual

CLOCK (4 MHz)
REFERENCE ONLY
ADDRESS
DATA (OUTPUT)
EXTERNAL WRITE
EXTERNAL OUTPUT
EXTERNAL READ
DATA (INPUT)
GATE EXT READY
EXTERNAL READY
-i
250
I-
----~(~------------~)~---------
---~( )~-------
~~------------'/
I
~~---~/
I
>0-1
10-
-----------I----------~(~:
___
)~------------
~:4~---750----~~~--,
________
~I----------t
\-----------
I
-I
1->0
NOTE: ALL TI MES I N NANOSECONDS.
Figure 4-13. External Input or Output Timing
(No Extra Wait states)
03340
Input Cycle - The processor places the address on the bus
(shown by drivers going from tristate floating to bipolar
state). Fifty nanoseconds later the External Read signal
goes active (low). At this time, the devices can start
sampling the address bus and the device that matches the
address code can start conditioning the external ready line
and turn the data drivers on (shown by the drivers going
from tristate floating to bipolar state).
The processor timing stops and the sequence is resumed by
the External Ready signal.
4-24
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